LDPC decoder
AssigneeSTMicroelectronics S.r.l.
InventorsPascal Urard, Laurent Paumier
Life of this patent
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Abstract
An LDPC decoder having a determined number of processing units operating in parallel, storage circuitry capable of containing first words containing a juxtaposition of messages of a first type, and second words containing a juxtaposition of messages of a second type, a message provision unit capable of providing each processing unit with a message of the first type or a message of the second type, and a message write unit capable of writing, into the storage circuitry, first words or second words. The message provision unit is capable of providing a message at a position in a word which depends on the word or the message write unit is capable of writing each message at a position in the word which depends on the word.
Claims20
An LDPC decoder that receives input words and provides output words to an output memory, the output words representing a decoding of the input words, the decoder comprising:
- a determined number of processing units operating in parallel, capable of receiving first messages and of providing second messages based on a processing of the first received messages;
- first and second single-port memories;
- first means for:
- reading first words both from the first single-port memory and from the second single-port memory, each first word comprising a juxtaposition of first messages in a number equal to said determined number;
- providing first messages to the processing units, each first message being based on at least one of the first words and/or at least one of the input words;
- forming second words, each second word comprising a juxtaposition of second messages provided by the processing units in a number equal to said determined number;
- and
- writing at least some of the second words into the first and second single-port memories, said first means being capable, for at least some of the first words and second words, of reading the at least some of the first words from the first single-port memory and of simultaneously writing the at least some of the second words into the second single-port memory or of reading the at least some of the first words from the second single-port memory and of simultaneously writing the at least some of the second words into the first single-port memory;
- and
- second means for providing the output words based, at least in part, on the second messages provided by the processing units.
An iterative LDPC decoding method for receiving input words and providing output words that represent a decoding of the input words, said method using a determined number of processing units operating in parallel, said method comprising:
- providing each processing unit with a first message based on at least one of the input words;
- reading first words both from a first single-port memory and from a second single-port memory, each first word comprising a juxtaposition of first messages in a number equal to the determined number;
- providing each processing unit, for each first word, with a first message based on the first word;
- providing, from each processing unit, second messages based on a processing of the first messages;
- writing at least some of the second words into the first and second single-port memories, each second word corresponding to a juxtaposition of second messages in a number equal to the determined number, for at least some of the first words and second words, the reading of the at least some of the first words from the first memory being performed simultaneously with the writing of the at least some of the second words into the second memory or the reading of the at least some of the first word from the second memory being performed simultaneously with the writing of the at least some of the second word into the first memory;
- and
- providing the output words based, at least in part. on the second messages provided by the processing units.
A method for implementing a low density parity check (LDPC) decoder using N processing units operating in parallel, the method comprising:
- receiving a set of input words comprising a first input word;
- forming N first input messages, based at least in part on a first processing of the first input word;
- providing the N first input messages to the N processing units to obtain N first output messages;
- forming a first output word, based at least in part on the N first output messages;
- writing the first output word into a first single-port memory and simultaneously reading a second input word from a second single-port memory;
- forming a second output word based at least in part on N second output messages provided by the N processing units;
- and
- providing a set of output words comprising the second output word, wherein the set of output words forms a decoding of the set of input words.
Dependencies are inferred from the claim text.