Method for testing semiconductor chips using register sets
AssigneeInfineon Technologies AG
InventorsUdo Hartmann, Jochen Kallscheuer, Patric Stracke
Life of this patent
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AssigneeInfineon Technologies AG
InventorsUdo Hartmann, Jochen Kallscheuer, Patric Stracke
Estimating the term…
A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.
A method for testing semiconductor chips, in which at least one test mode is set in a chip which is to be tested and has a test logic unit, the test mode is executed in the chip, and a status of the test mode or test results are output from the chip, the method comprising:
A method for testing semiconductor chips, in which at least one test mode is set in a chip which is to be tested and has a test logic unit, the test mode is executed in the chip, and a status of the test mode or test results are output from the chip, the method comprising:
Dependencies are inferred from the claim text.