Testing of a programmable device

A field programmable gate array (FPGA) comprises:

• an input/output section;
• programmable logic fabric operably coupled to the input/output section;
• and
• memory operably coupled to the programmable logic, wherein the FPGA is tested by:
• programming at least a portion of the FPGA device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element;
• providing a test input to the programmed circuit;
• triggering the input sequential element to temporarily store the test input based on a first edge of the test clock;
• triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock;
• capturing the test output of the programmed circuit in accordance with the second edge of the test clock;
• and
• wherein a pulse width defined by the first and second edges of the test clock is adjusted to determine an amount of time required for a logic transition of the test output to occur.