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US 7,454,672 B2Granted
Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-Cheol Lee, Su-Chul Kim, Uk-Rae Cho
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Abstract
Provided is a semiconductor memory device testable with a single data rate (SDR) or a dual data rate (DDR) pattern in a merged data input/output pin (DQ) test mode. The device includes a first path circuit, a second path circuit, and a merged output generator configured to generate a merged data bit having a SDR and/or DDR pattern.
Claims16
A semiconductor memory device operable in a merged data input/output pin (DQ) test mode, comprising:
- a first path circuit receiving a first data bit, a second single data rate (SDR) signal, and a first transmission signal pair and producing a first path output signal and including a first switching element controlled by the second single data rate signal;
- a second path circuit receiving a second data bit, a first single data rate signal, and a second transmission signal pair and producing a second path output signal and including a second switching element controlled by the first single data rate signal;
- and
- a merged output generator configured to generate a merged data bit based on the first path output signal and the second path output signal having a single data rate (SDR) pattern and/or a dual data rate (DDR) pattern, as determined by the first single data rate signal fed to the second switching element and the second single data rate signal fed to the first switching element and the first and second transmission signal pairs.
1 more element
A semiconductor memory device for operating in a merged data input/output pin (DQ) test mode, comprising:
- a control signal generator for generating first and second single data rate (SDR) signals and first and second transmission signal pairs, wherein each signal of a pair is complementary to the other signal of the pair;
- a first path circuit for receiving the second single data rate signal and one of the first and second transmission pairs and including a first switching element controlled by the second single data rate signal;
- a second path circuit for receiving the first single data rate signal and the other of the first and second transmission pairs and including a second switching element controlled by the first single data rate signal;
- and
- a merged output generator for generating a merged data bit, wherein the merged data bit has an SDR or dual data rate (DDR) pattern depending upon the first single data rate signal fed to the second switching element and the second single data rate signal fed to the first switching element as determined by a respective plurality of output clock signals fed to the control signal generator.
2 more elements
Dependencies are inferred from the claim text.