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US 7,454,666 B1Granted
Real-time address trace generation
AssigneeSun Microsystems, Inc.
InventorsPaul J. Jordan, Joseph T. Rahmeh, Gregory F. Grohoski
Life of this patent
Estimating the term…
Abstract
A method for tracing of instructions executed by a processor is provided which includes providing a type of instruction to be traced and tracing at least one instruction corresponding to the type of instruction. The method further includes storing data without stopping from the tracing into a memory until the memory is full.
Claims20
A method for tracing of instructions executed by a processor, comprising:
- identifying a type of processor instruction to be traced by a particular thread separately from other types of processor instructions, the particular thread being assigned to particular trace registers within a memory management unit (MMU) of the processor, for each thread, the trace registers include trace configuration type register, a trace size register, and a trace address register;
- allocating a trace address allocation buffer in cache memory of the processor for each type of processor instruction;
- enabling parallel execution of multiple threads, for each thread, tracing at least one instruction corresponding to the type of processor instruction;
- and
- storing at least one address corresponding to the at least one instruction from the tracing into the cache memory of the processor, the storing continuing until the cache memory is full up to the size identified by the trace size register.
2 more elements
A method for tracing of instructions executed by a processor, comprising:
- storing a type of instruction to be traced by a particular thread separately from other types of processor instructions, the particular thread being assigned to particular trace registers within a memory management unit (MMU) of the processor, for each thread, the trace registers include a trace configuration type register, a trace size register, and a trace address register;
- enabling parallel execution of multiple threads, for each thread, tracing at least one instruction corresponding to the type of processor instruction stored in the trace configuration type register within the memory management unit (MMU) of the processor;
- and
- storing data from the tracing into a cache memory of the processor until the cache memory is full up to the size identified by the trace size register, the storing including decrementing a counter for each address stored in the cache memory and stopping the tracing when the counter is zero.
1 more element
A processor, comprising:
- within the processor,
- (a) a memory management unit (MMU) having a trace state machine, the trace state machine including trace registers defined by a trace configuration type register, a trace size register, and a trace address register, the MMU including a multiplexer and a hardware tablewalk;
- (b) an arithmetic logic unit (ALU) configured to process instructions of multiple threads;
- (c) a trap logic unit coupled to the ALU and the multiplexer of the MMU;
- (d) a load/store unit (LSU) coupled to the ALU and the multiplexer of the MMU, the MMU configured to trace an instruction processed by the ALU by following output of the TLU and LSU for a particular thread separately from other types of processor instructions, each type of processor instruction being correlated with a set of the trace registers that include the trace configuration type register, the trace size register, and the trace address register, such that multiple threads execute in parallel with corresponding trace registers;
- and
- (e) a cache memory holding one or more trace buffers, and each trace buffer being linked to an output of the multiplexer, and the hardware tablewalk providing translation between the MMU and the cache memory, and each trace buffer being correlated to particular trace registers that correspond to particular threads, such that the trace buffers have a size defined by the corresponding trace size register.
4 more elements
Dependencies are inferred from the claim text.