Marginless status determination circuit
AssigneeFujitsu Limited
InventorsKenji Yoshida, Yoshihiko Koike, Tetsuya Yoshida
Life of this patent
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Abstract
By including a unit for storing data to be determined, a unit for delaying the data, a unit for storing the output of the delay unit, and a unit for comparing the storage contents of the data before the delay with the storage contents of the data after the delay, and outputting a marginless status detection signal when they are different, the presence/absence of a margin is monitored regardless of ambient conditions by using an output marginless status detection signal as a switch control signal for a clock switch circuit, thereby operating electronic equipment without changing a frequency of a clock signal up to the critical condition.
Claims11
A determination circuit which determines presence/absence of a margin of a data delay, comprising:
- a first data storage unit storing data;
- a data delay unit delaying the data;
- a second data storage unit storing output of the data delay unit;
- and
- a comparison unit comparing storage contents of the first data storage unit with storage contents of the second data storage unit, and outputting a marginless status detection signal when the contents are different;
- wherein the marginless status detection signal output by the comparison unit is used as a switch control signal to a clock switch circuit;
- and
- a clock signal switched by the clock switch circuit, depending on input of the marginless status detection signal, is provided for a central processing device of a microcomputer.
A determination circuit which determines presence/absence of a margin of a data delay, comprising:
- a data storage unit storing data;
- a plurality of data delay units delaying the data by respective different delay times;
- a plurality of delay data storage unit respectively storing output of the plurality of date delay units;
- a plurality of comparison units comparing respective storage contents of the plurality of delay data storage units with respective storage contents of the data storage units, and outputting a nonmatching detection signal when the storage contents are different;
- and
- a clock switch unit switching clock signals having different frequencies based on an output value of the plurality of comparison units;
- wherein a clock signal switched by the clock switch circuit is provided for a central processing device of a microcomputer.
Dependencies are inferred from the claim text.