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US 7,454,646 B2Granted
Efficient clocking scheme for ultra high-speed systems
AssigneeMicron Technology, Inc.
InventorFeng Lin
Life of this patent
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Abstract
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.
Claims19
A device comprising:
- a clock divider and generator circuit configured to divide an input signal and to generate three clock signals, wherein the three clock signals comprise:
- a first clock signal having a rising edge and a falling edge;
- a second clock signal having a rising edge and a falling edge, wherein the rising edge of the second clock signal occurs concurrently with the falling edge of the first clock signal;
- and
- a third clock signal having a rising edge and a falling edge, wherein the rising edge of the third clock signal occurs concurrently with the falling edge of the second clock signal;
- a clock selection circuit coupled to an output of the clock divider circuit and configured to receive the three clock signals and to select one of the clock signals based on the phase relationship with the input signal;
- a delay-lock loop coupled to an output of the clock selection circuit configured to place the selected clock signal in phase with the input signal;
- and
- a feedback model circuit configured to provide a feedback signal to the clock selection circuit.
6 more elements
A device comprising:
- a clock divider and generator circuit configured to divide an input signal and to generate three clock signals, wherein the clock divider and generator comprises true single phase logic:
- a clock selection circuit coupled to an output of the clock divider circuit and configured to receive the three clock signals and to select one of the clock signals based on the phase relationship with the input signal;
- a delay-lock loop coupled to an output of the clock selection circuit configured to place the selected clock signal in phase with the input signal;
- and
- a feedback model circuit configured to provide a feedback signal to the clock selection circuit.
2 more elements
A device comprising:
- means for receiving an input signal;
- means for dividing the input signal to produce a divided input signal;
- means for generating three clock signals from the divided input signal, wherein the three clock signals comprise:
- a first clock signal having a rising edge and a falling edge;
- a second clock signal having a rising edge and a falling edge, wherein the rising edge of the second clock signal occurs concurrently with the falling edge of the first clock signal;
- and
- a third clock signal having a rising edge and a falling edge, wherein the rising edge of the third clock signal occurs concurrently with the falling edge of the second clock signal;
- means for selecting one of the three clock signals based on a phase relationship of the selected clock signal to the input signal;
- and
- means for synchronizing the selected signal with the input signal.
7 more elements
A method comprising:
- receiving an input signal;
- deriving three output signals from the input signal;
- selecting one of the three output signals based on a phase characteristics of each of the three output signals relative to the input signal;
- and
- synchronizing the selected output signal with the input signal, wherein synchronizing the selected output signal comprises synchronizing the selected output signal with the input signal in less than or equal to two clock periods of the input signal.
2 more elements
A method of synchronizing signals comprising:
- receiving an input signal in a memory device;
- dividing the input signal by 3 or 6 to produce a divided input signal;
- generating three output signals from the divided input signal, wherein generating three output signals comprises generating three output signals that are separated by one clock period of the input signal if the input signal is divided by 3 and two clock periods of the input signal if the input signal is divided by 6;
- selecting one of the three output signals based on a phase relationship of the selected output signal to the input signal;
- and
- synchronizing the selected output signal with the input signal using a delay lock loop.
3 more elements
Dependencies are inferred from the claim text.