Circuit and method for monitoring the status of a clock signal
AssigneeCypress Semiconductor Corporation
InventorsGabriel M. Li, Greg J. Richmond, Sangeeta Raman
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Abstract
A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.
Claims19
A method for monitoring the status of a clock signal, the method comprising:
- supplying a first clock signal and a second clock signal to a clock monitor circuit;
- and
- monitoring a status of the first clock signal relative to the second clock signal, wherein the status indicates whether a frequency of the first clock signal is FASTER, SLOWER, or substantially EQUIVALENT TO a frequency of the second clock signal, and wherein the step of monitoring comprises:
- counting a number of pulses, X, associated with the first clock signal and a number of pulses, Y, associated with the second clock signal until the Y-number of pulses reaches a predetermined maximum count value;
- and
- determining the status of the first clock signal relative to the second clock signal by comparing the X-number of pulses with the Y-number of pulses, wherein the status is determined to be:
- FAST, if the X-number of pulses is substantially greater than the Y-number of pulses;
- EQUIVALENT, if the X-number of pulses is substantially equal to the Y-number of pulses;
- and
- SLOW, if X-number of pulses is substantially less than the Y-number of pulses.
A method for determining the status of a first clock signal relative to a second clock signal, the method comprising:
- counting a number of pulses X associated with the first clock signal, and a number of pulses Y associated with the second clock signal, until the Y-number of pulses reaches a predetermined maximum count value;
- storing the X-number of pulses as a bit pattern within an M-bit storage element and the Y-number of pulses as another bit pattern within an N-bit storage element, where N=M-1;
- determining the status of the first clock signal relative to the second clock signal by detecting a logic state of using one or more bits stored within the M-bit storage element, wherein the status is determined to be:
- FAST, if a most significant bit of the M-bit storage element is a logic 1;
- EQUIVALENT, if the most significant bit of the M-bit storage element is a logic 0 and the next Z-number of bits within the M-bit storage element are each logic 1;
- or
- SLOW, if the most significant bit of the M-bit storage element is a logic 0 and at least one of the next Z-number of bits within the M-bit storage element is a logic 0.
A circuit for monitoring the status of a clock signal, the circuit comprising:
- an M-bit counter for counting a number of clock pulses X occurring within a first clock signal supplied to the circuit;
- an N-bit counter for counting a number of clock pulses Y occurring within a second clock signal supplied to the circuit, where N=M-1;
- and
- control logic for determining if the N-bit counter has reached a predetermined maximum count, and if so, using one or more bits stored within the M-bit and N-bit counters to determine the status of the first clock signal relative to the second clock signal, wherein the status indicates whether a frequency of the first clock signal is FASTER, SLOWER, or substantially EQUIVALENT TO a frequency of the second clock signal.
Dependencies are inferred from the claim text.