Power saving device and electronic device using the same
AssigneeOnkyo Corporation
InventorsKazunari Ito, Tadaharu Sunaga
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AssigneeOnkyo Corporation
InventorsKazunari Ito, Tadaharu Sunaga
Estimating the term…
A microcomputer 11 stays in a power saving mode until a remote control signal is input and a first interrupt signal is input to an interrupt terminal 14. When the first interrupt signal is input, the microcomputer 11 performs an intermittent operation in which the power saving mode and the normal mode are periodically alternated with each other, and ends the intermittent operation when the remote control signal is received completely. After the intermittent operation, the microcomputer 11 stays in the normal mode if the remote control signal is a power-requesting signal and stays in the power saving mode otherwise.
A power saving device operable in a power saving mode and in a normal mode, comprising a controller including an interrupt terminal for receiving a first interrupt signal based on an input remote control signal, wherein:
A power saving device operable in a power saving mode and in a normal mode, comprising a controller including an interrupt terminal for receiving a first interrupt signal based on an input remote control signal, wherein:
An electronic device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Means for saving power: power management, i.e. event-based initiation of a power-saving mode
Computing and data processing
About 2 months of term left · ends 28 Dec 2026 (estimated)
1. Field of the Invention
The present invention relates to a power saving device in which a microcomputer is shut down in a standby state.
2. Description of the Related Art
FIG. 1 is a block diagram showing a power saving device according to a preferred embodiment of the present invention.
FIG. 2A and FIG. 2B are timing charts each showing an operation of the power saving device of the preferred embodiment.
FIG. 3 is a flow chart showing an operation of the power saving device of the preferred embodiment.
While a preferred embodiment of the present invention will now be described with reference to the drawings, it is understood that the present invention is not limited thereto. FIG. 1 is a schematic block diagram showing a power saving device 10 according to the preferred embodiment of the present invention. The power saving device 10 includes a controller 11 and a remote control signal receiving circuit 12, and transitions from the power saving mode to the normal mode in response to a received interrupt signal. The power saving device 10 can be used in a common electronic device such as a CD player.
The controller 11 controls the overall operation of an electronic device (e.g., a CD player) with which the power saving device 10 can be used (i.e., it controls a controlled section 15), and is typically a microcomputer, for example. The microcomputer 11 includes a memory 13 (e.g., a ROM and/or a RAM), which may be provided in the microcomputer 11 or may be provided outside and connected to the microcomputer 11 via a bus, or the like. The microcomputer 11 executes various programs stored in the memory 13 to perform various operations (e.g., bringing a CD player to the Play mode). The microcomputer 11 includes a main circuit 16 for controlling the controlled section 15, an oscillator circuit 17 and a timer circuit 18. The oscillator circuit 17 produces a clock signal, and supplies the produced clock signal to the main circuit 16 and the timer circuit 18. The timer circuit 18 receives the clock signal from the oscillator circuit 17, and counts a predetermined amount of time based on the clock signal. Specifically, the timer circuit 18 counts a predetermined amount of time by counting the number of pulses of the clock signal. Upon completion of the counting of a predetermined amount of time, the timer circuit 18 gives a second interrupt signal to the main circuit 16. The second interrupt signal is used for triggering the transition to the normal mode in the intermittent operation to be described later. The main circuit 16 receives the clock signal from the oscillator circuit 17 and performs various operations. Moreover, the main circuit 16 instructs the oscillator circuit 17 to stop the supply of the clock signal, and/or instructs the timer circuit 18 to start/stop the count operation.
The power saving device 10 has a so-called “standby mode” in which the power is supplied only to the microcomputer 11, the memory 13 and the remote control signal receiving circuit 12 so that the main power can be turned ON by a user's operation of the remote control. Specifically, the main power supply is electrically connected to the power saving device 10 as a whole, whereas the standby power supply is electrically connected only to the microcomputer 11, the memory 13 and the remote control signal receiving circuit 12. In the standby state, the main power is OFF, and only the standby power is ON. An OFF state as used herein refers to a state where the power is not being supplied as it is stopped by a switch (not shown), for example, being open, and an ON state as used herein refers to a state where the power is being supplied through the switch being closed.