Electronic data processing device
AssigneeAtos Worldline SA
InventorsPeter Timmermans, Carl Van Himbeeck, Marc Moons
Life of this patent
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AssigneeAtos Worldline SA
InventorsPeter Timmermans, Carl Van Himbeeck, Marc Moons
Estimating the term…
An electronic data processing device, comprising an access protected memory, provided for storing secure data and a data processing member, provided for processing said secure data, said terminal comprises a tampering detection and protection circuit provided for detecting a tamper condition and for generating a tamper signal upon detection of said tamper condition, said tampering detection and protection circuit being connected to a tampering sequencer, provided for disabling said processing member upon receipt of said tampering signal, said memory comprises a security register provided for storing keys for encrypting said secure data and a memory section provided for storing keys for encrypting said secure data and a memory section provided for temporarily storing secure data processed by said data processing member, said tampering sequencer comprises an internal clock generator provided for generating, upon receipt of said tamper signal a tamper pulse and a series of clock pulses, said tampering sequencer being provided for erasing under control of said tamper pulse, said security data stored in said security register and for erasing, under control of said series of clock pulses said processed secure data stored in said memory section.
An electronic data processing device, comprising an access protected memory, provided for storing secure data, in particular data related to a fund transfer, and a data processing member connected to said memory via a bus and provided for processing said secure data, said memory comprises a security register provided for storing keys for encrypting said secure data and a memory section provided for temporarily storing secure data processed by said data processing member, said electronic data processing device comprising furthermore a tampering detection and protection circuit connected to said bus and provided for detecting a tamper condition and for generating a tamper signal upon detection of said tamper condition, said tampering detection and protection circuit being connected to a tampering sequencer, provided for disabling said processing member upon receipt of said tampering signal, said tampering sequencer comprises an internal clock generator provided for generating, upon receipt of said tamper signal a tamper pulse and a series of clock pulses, said tampering sequencer being provided for erasing under control of said tamper pulse, said security data stored in said security register and for erasing, under control of said series of clock pulses said processed secure data stored in said memory section.
Dependencies are inferred from the claim text.