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US 7,454,601 B2Granted
N-wide add-compare-select instruction
AssigneeIntel Corporation
InventorGad Sheaffer
Life of this patent
Estimating the term…
Abstract
The present invention relates to a method and system for providing an N-wide add-compare-select instruction includes decoding an instruction as an N-wide add-compare-select instruction and selecting a plurality of branch metrics. The method also includes combining the plurality of branch metrics with a plurality of source operands and outputting a pair of maximum values.
Claims26
A method for providing an instruction, the method comprising:
- decoding an instruction with a decoder in a processor device as an N-wide add-compare-select instruction, said decoding operation comprises decoding said N-wide add-compare-select instruction as a quad add-compare-select instruction, said quad add-compare-select instruction having a plurality of operands;
- selecting a plurality of branch metrics;
- combining the plurality of branch metrics with a plurality of source operands wherein one of said plurality of branch metrics is combined with at least two source operands of said instruction;
- outputting a pair of maximum values of values from said combining operation;
- and
- updating a plurality of control registers, if requested by said N-wide add-compare-select instruction wherein said updating operation comprises:
- rotating an operand selection register (OSR) four bits to the right;
- and
- rotating a polarity setting register (PSR) two bits to the right.
6 more elements
A processor, said processor comprising:
- a decoder to decode instructions, said decoder to decode a quad add-compare-select instruction having a plurality of operands;
- and
- a circuit coupled to said decoder, said circuit, in response to a decoded instruction, to select a plurality of branch metrics,
- combine the plurality of branch metrics with a plurality of source operands wherein one of said plurality of branch metrics is combined with at least two source operands of said instruction,
- output a pair of maximum values of the combined values,
- update a plurality of control registers, if requested by said quad add-compare- select instruction, the update including
- rotate an operand selection register (OSR) four bits to the right;
- and
- rotate a polarity setting register (PSR) two bits to the right.
6 more elements
A computer system comprising:
- a processor;
- and
- a machine-readable medium coupled to the processor, the instructions which, when executed, configure the processor to
- decode an instruction as a quad add-compare-select instruction, said quad add-compare-select instruction having a plurality of operands;
- select a plurality of branch metrics;
- combine the plurality of branch metrics with a plurality of source operands wherein one of said plurality of branch metrics is combined with at least two source operands of said instruction;
- output a pair of maximum values of the combined values;
- update a plurality of control registers, if requested by said quad add-compare-select instruction, the update including
- rotate an operand selection register (OSR) four bits to the right;
- and
- rotate a polarity setting register (PSR) two bits to the right.
8 more elements
A machine-readable medium in which is stored one or more instructions adapted to be executed by a processor, the instructions which, when executed, configure the processor to
- decode an instruction as a quad add-compare-select instruction, said quad add-compare-select instruction having a plurality of operands;
- select a plurality of branch metrics;
- combine the plurality of branch metrics with a plurality of source operands wherein one of said plurality of branch metrics is combined with at least two source operands of said instruction;
- output a pair of maximum values,
- update a plurality of control registers, if requested by said quad add-compare-select instruction, the update including
- rotate an operand selection register (OSR) four bits to the right;
- and
- rotate a polarity setting register (PSR) two bits to the right.
5 more elements
Dependencies are inferred from the claim text.