Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements

An arithmetic instruction processing method used in a processor comprising a plurality of registers each of which includes only one first part and only one second part, said first part registering high-order bits and said second part registering low-order bits, said method comprising the steps of:

• providing an arithmetic unit with a data width of (a) bits being used as a plurality of (b)-bit arithmetic units to simultaneously process a SIMD instruction on a plurality of discrete elements in each of the (b)-bit arithmetic units respectively, (a) and (b) being positive integers, and (a) being a multiple of (b);
• performing a first arithmetic operation on data in the first parts of said plurality of registers and a second arithmetic operation on data in the second parts of said plurality of registers with the arithmetic unit, the first arithmetic operation and the second arithmetic operation being performed according to the SIMD instruction simultaneously;
• executing operations according to the SIMD instruction, the SIMD instruction comprising an operand that designates, independently and respectively, only the first part of one of the plurality of registers to store a result of the first arithmetic operation and only the second part of another one of the plurality of registers to store a result of the second arithmetic operation;
• and
• storing the result of said first arithmetic operation into said only one of the first parts of said plurality of registers and the result of the second arithmetic operation into said only one of the second parts of the plurality of registers according to the operand of the SIMD instruction.