Data buffer circuit, interface circuit and control method therefor

A data buffer circuit which is interposed between a synchronous circuit and an asynchronous circuit that conducts a read access or a write access in an active period of a read control signal or a write control signal, and buffers data transfer between the synchronous circuit and the asynchronous circuit, the data buffer circuit comprising:

• an interface circuit that inputs the read control signal and the write control signal of the asynchronous circuit and outputs a clock signal in response to the read control signal and the write control signal;
• and
• a synchronous memory circuit that conducts a data access with respect to the synchronous circuit in synchronization and conducts the data access with respect to the asynchronous circuit in synchronization with a clock signal outputted from the interface circuit,
• wherein the interface circuit includes a clock signal generating section that generates the clock signal with the termination edges of the respective active periods in the read control signal and the write control signal as the active edges, a subsequent cycle address generating section that generates a present cycle address which is an address corresponding to an access from the asynchronous circuit and a subsequent cycle address which is an address of a subsequent access cycle of the present cycle address in the continuous access cycles to the synchronous circuit, and a first address selecting section that selects any one of the subsequent cycle address and the present cycle address as an address of the synchronous memory circuit according to a command from the asynchronous circuit, and
• wherein the first address selecting section selectively outputs the present cycle address when the access to the synchronous memory circuit is the write access, and selectively outputs the subsequent cycle address when the access to the synchronous memory circuit is the read access.

A data buffer circuit which is interposed between a synchronous circuit and an asynchronous circuit that conducts a read access or a write access in an active period of a read control signal or a write control signal, and buffers data transfer between the synchronous circuit and the asynchronous circuit, the data buffer circuit comprising:

• an interface circuit that inputs the read control signal and the write control signal of the asynchronous circuit and outputs a clock signal in response to the read control signal and the write control signal;
• and
• a synchronous memory circuit that conducts a data access with respect to the synchronous circuit in synchronization and conducts the data access with respect to the asynchronous circuit in synchronization with a clock signal outputted from the interface circuit,
• wherein the synchronous memory circuit comprises a synchronous dual port memory circuit having a write address input terminal used in the write access and a read address input terminal used in the read access, individually,
• wherein the interface circuit includes a clock signal generating section that generates the clock signal with the termination edges of the respective active periods in the read control signal and the write control signal as the active edges and a subsequent cycle address generating section that generates a present cycle address which is an address corresponding to an access from the asynchronous circuit and a subsequent cycle address which is an address of a subsequent access cycle of the present cycle address in the continuous access cycles to the synchronous circuit, and
• wherein the synchronous dual port memory circuit inputs the present cycle address from the write address input terminal, and inputs the subsequent cycle address from the read address input terminal.

A method of controlling an interface circuit that is interposed between a synchronous circuit that conducts a data access in synchronization with an active edge of a clock signal and an asynchronous circuit that conducts a read access or a write access in an active period of a read control signal or a write control signal, and controls the synchronous circuit according to the read control signal or the write control signal outputted from the asynchronous circuit, the method comprising the steps of:

• generating the clock signal having termination edges of the respective active periods in the read control signal and the write control signal as the active edges;
• generating a present cycle address that is an address corresponding to the access from the asynchronous circuit, and a subsequent cycle address that is an address of a subsequent access cycle of the present cycle address in sequential access cycles to the synchronous circuit;
• and
• selecting any one of the subsequent cycle address and the present cycle address according to a command from the asynchronous circuit as an address of the synchronous circuit,
• wherein the step of selecting the address of the synchronous circuit selectively outputs the present cycle address when the access to the synchronous circuit is the write access, and selectively outputs the subsequent cycle address when the access to the synchronous circuit is the read access.