Efficient and flexible memory copy operation

A system for semi-synchronously copying data from a first portion of memory to a second portion of memory, the system comprising:

• a memory;
• a first level of cache memory;
• a second level of cache memory;
• at least a third level of cache memory;
• a memory controller communicatively coupled to the memory;
• a processor communicatively coupled to the memory and the memory controller, wherein the processor receives a call for a semi-synchronous memory copy operation associated with the memory which preserves temporal persistence of validity for a virtual source address corresponding to a source location in the memory and a virtual target address corresponding to a target location in the memory by setting a flag bit, wherein a length of the semi-synchronous memory copy operation is arbitrarily defined, and wherein an address range corresponding to the virtual source address and an address range corresponding to the virtual target address are un-aligned where a set of memory pages referenced by the virtual source address and the virtual target address are pageable, wherein preserving temporal persistence of validity includes preventing a load operation to the source location and the target location during the semi-synchronous memory copy operation and preventing a store operation to the target location during the semi-synchronous memory copy operation,
• the call including at least the virtual source address, the virtual target address, an indicator identifying a number of bytes to be copied, and a cache injection bit comprising a given value indicating a given number of lines of destination data, which correspond to the number of bytes, that are to be transferred to a given number of cache levels, wherein the semi-synchronous memory copy operation operates semi-synchronously with the processor to provide maximum processor utilization such that the processor is able to execute at least one additional instruction on the memory during the semi-synchronous memory copy operation;
• and
• a queue for holding the semi-synchronous memory copy operation for execution by the memory controller, wherein the queue is coupled to the memory controller;
• wherein the processor is adapted to execute, in response to the semi-synchronous memory copy operation being held in the queue, the semi-synchronous memory copy operation, wherein executing the semi-synchronous memory copy operation includes:
• copying, based on the cache injection bit, a first predefined number of lines of destination data into a first level of cache memory, a second predefined number of lines of destination data that is subsequent and sequential to the first predefined number of lines of destination data to a second level of cache memory, and at least a third predefined number of lines of destination data that is subsequent and sequential to the second predefined number of lines of destination data to at least a third level of cache memory;
• copying a remainder of destination data that has not been transferred to a level of cache memory from the source memory location to the target memory location within the memory;
• moving at least one line of destination data from the at least third level of cache memory to the second level of cache memory and at least one line of destination data from the second level of cache memory to the first level of cache memory in response to a least one of the first predefined number of lines of destination data being accessed in the first level of cache memory, wherein the at least one line of destination data being moved from the third level of cache memory to the second level of cache memory and the at least one line of destination data being moved from the second level of cache memory to the first level of cache memory are moved in a sequential manner;
• wherein the processor is further adapted to execute at least one subsequent instruction on the memory during the semi-synchronous memory copy operation as the subsequent instruction becomes available from an instruction pipeline, continuing to execute the at least one subsequent instruction includes
• determining whether the subsequent instruction is for at least one of
• reading from at least one of:
• a source address range;
• and
• a destination address range;
• and
• writing to at least one of:
• the source address range;
• and
• the destination address range,
• executing by the processor the subsequent instruction in response to the subsequent instruction being for reading from the source address range;
• and
• wherein temporal persistence of validity is preserved for the source destination range and the destination address range during an ongoing semi-synchronous memory copy operation;
• determining if the queue comprising the semi-synchronous memory copy operation is full;
• placing in the queue at least one additional semi-synchronous memory copy operation for execution by the memory controller in response to the queue having space for the additional semi-synchronous memory copy operation;
• and
• waiting to place in the queue the at least one additional semi-synchronous memory copy operation in response to the queue being full until the queue has enough space for the at least one additional semi-synchronous memory copy operation.

A computer program product for or semi-synchronously copying data from a first portion of memory to a second portion of memory, the computer program product on an information processing system comprising:

• a computer readable storage medium readable by the information processing system, the computer readable storage medium instructions for performing:
• receiving, in a processor, a call for a semi-synchronous memory copy operation associated with a memory which preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit, wherein a length of the semi-synchronous memory copy operation is arbitrarily defined, and wherein an address range corresponding to the virtual source address and an address range corresponding to the virtual target address are un-aligned where a set of memory pages referenced by the virtual source address and the virtual target address are pageable, wherein preserving temporal persistence of validity includes preventing a load operation to the source location and the target location during the semi-synchronous memory copy operation and preventing a store operation to the target location during the semi-synchronous memory copy operation,
• the call including at least the virtual source address, the virtual target address, an indicator identifying a number of bytes to be copied, and a cache injection bit comprising a given value indicating a given number of lines of destination data, which correspond to the number of bytes, that are to be transferred to a given number of cache levels, wherein the semi-synchronous memory copy operation operates semi-synchronously with the processor to provide maximum processor utilization such that the processor is able to execute at least one additional instruction on the memory during the semi-synchronous memory copy operation;
• placing in a queue the semi-synchronous memory copy operation for execution by a memory controller, wherein the queue is coupled to the memory controller;
• executing, in response to placing the semi-synchronous memory copy operation in the queue, the semi-synchronous memory copy operation, wherein executing the semi-synchronous memory copy operation includes:
• copying, based on the cache injection bit, a first predefined number of lines of destination data into a first level of cache memory, a second predefined number of lines of destination data that is subsequent and sequential to the first predefined number of lines of destination data to a second level of cache memory, and at least a third predefined number of lines of destination data that is subsequent and sequential to the second predefined number of lines of destination data to at least a third level of cache memory;
• copying a remainder of destination data that has not been transferred to a level of cache memory from the source memory location to the target memory location within the memory;
• moving at least one line of destination data from the at least third level of cache memory to the second level of cache memory and at least one line of destination data from the second level of cache memory to the first level of cache memory in response to a least one of the first predefined number of lines of destination data being accessed in the first level of cache memory, wherein the at least one line of destination data being moved from the third level of cache memory to the second level of cache memory and the at least one line of destination data being moved from the second level of cache memory to the first level of cache memory are moved in a sequential manner;
• continuing to execute at least one subsequent instruction on the memory during the semi-synchronous memory copy operation as the subsequent instruction becomes available from an instruction pipeline, continuing to execute the at least one subsequent instruction includes
• determining whether the subsequent instruction is for at least one of
• reading from at least one of:
• a source address range;
• and
• a destination address range;
• and
• writing to at least one of:
• the source address range;
• and
• the destination address range,
• executing by the processor the subsequent instruction in response to the subsequent instruction being for reading from the source address range;
• and
• wherein temporal persistence of validity is preserved for the source destination range and the destination address range during an ongoing semi-synchronous memory copy operation:
• determining if the queue comprising the semi-synchronous memory copy operation is full;
• placing in the queue at least one additional semi-synchronous memory copy operation for execution by the memory controller in response to the queue having space for the additional semi-synchronous memory copy operation;
• and
• waiting to place in the queue the at least one additional semi-synchronous memory copy operation in response to the queue being full until the queue has enough space for the at least one additional semi-synchronous memory copy operation.