Cache memory and its controlling method
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsRyuta Nakanishi, Hazuki Okabayashi, Tetsuya Tanaka, Shuji Miyasaka
Life of this patent
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Abstract
The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.
Claims11
A cache memory, comprising:
- a flag holding unit which holds, in a correspondence with a cache entry that holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into;
- a command holding unit which is configured of a register that allows access from a processor by a data transfer instruction, and holds a command issued by the processor by a data transfer instruction;
- and
- an altering unit operable to alter, based on a command held by said command holding unit, at least one of the valid flag and the dirty flag, contrary to the state of the cache entry, wherein the command to said command holding unit is issued by a data transfer instruction, the command being data transferred by the data transfer instruction, said altering unit operating independently of an operation of the processor, and performs the altering while the cache memory is not accessed by the processor.
A method for controlling a cache memory having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into, the cache entry holding a data unit of caching, the method comprising:
- causing a predetermined register to hold a command issued by a processor, the processor executing a data transfer instruction that transfers data as the command to the predetermined register;
- setting, in the cache entry, an address serving as a tag, and setting the valid flag, without loading data from a memory, based on a held command;
- and
- resetting, based on a held command, the dirty flag of the cache entry in a state in which the cache entry holds rewritten data that has not been written back, wherein setting the valid flag and resetting the dirty flag are performed independently of an operation of the processor, and are performed while the cache memory is not accessed by the processor.
Dependencies are inferred from the claim text.