Filtering bit position in a memory
AssigneeInfineon Technologies AG
InventorStefan Dietrich
Life of this patent
Estimating the term…
Abstract
A memory includes a plurality of first-in-first-out (FIFO) cells, an output pointer counter, a write training block and a temporary data register. The output pointer counter is for switching a value of a FIFO output pointer among the FIFO cells. The write training block is for moving the FIFO output pointer based on data read from the FIFO cells. The temporary data register is for storing a single bit representing one or more bits in each FIFO cell.
Claims30
A memory, comprising:
- a plurality of first-in-first-out (FIFO) cells;
- an output pointer counter for switching a value of a FIFO output pointer among the FIFO cells;
- a write training block for generating information for moving the FIFO output pointer based on data read from the FIFO cells;
- and
- a temporary data register for storing a single bit representing one or more bits in each FIFO cell.
A memory, comprising:
- a plurality of first-in-first-out (FIFO) cells for accepting a data pattern;
- an output pointer counter for switching a value of a FIFO output pointer among the FIFO cells in response to an external clock;
- a write training block for extending a write cycle for reading out all the FIFO cells, for determining whether the data pattern is located in a correct position in the FIFO cells, and for generating information for moving the FIFO output pointer from one FIFO cell to another FIFO cell if it is determined that the data pattern is located in the incorrect position;
- and
- a temporary data register for storing a single bit of data for each FIFO cell, wherein the single bit is a representation of the content of each FIFO cell.
A method of synchronizing a write data strobe clock signal with an external clock signal, comprising:
- writing a data pattern into a first-in-first-out (FIFO) buffer;
- reading out contents of the entire FIFO buffer;
- determining a single bit to represent the contents of each cell in the FIFO buffer;
- inverting the single bits;
- receiving a value of a FIFO output pointer at the beginning of the reading out contents of the entire FIFO buffer;
- executing a logical AND on the inverted bits and the value of the FIFO output pointer;
- and
- shifting the FIFO output pointer if the result of executing the logical AND is only zeros.
A method of synchronizing a write data strobe clock signal with an external clock signal, comprising:
- (a) writing a data pattern into a first-in-first-out (FIFO) buffer;
- (b) reading out contents of the entire FIFO buffer;
- (c) determining a single bit to represent the contents of each cell in the FIFO buffer;
- (d) inverting the single bits;
- (e) receiving a value of a FIFO output pointer at the beginning of the reading out contents of the entire FIFO buffer;
- (f) executing a logical AND on the inverted bits and the value of the FIFO output pointer;
- (g) shifting the FIFO output pointer if the result of executing the logical AND is only zeros;
- and
- (h) repeating (a) to (g) until the result of (f) provides a one.
A random access memory, comprising:
- means for writing a data pattern into a first-in-first-out (FIFO) buffer;
- means for reading out contents of the entire FIFO buffer;
- means for determining a single bit to represent the contents of each cell in the FIFO buffer;
- means for inverting the single bits;
- means for receiving a value of a FIFO output pointer at the beginning of the reading out contents of the entire FIFO buffer;
- means for executing a logical AM) on the inverted bits and the value of the FIFO output pointer;
- and
- means for shifting the FIFO output pointer if the result of executing the logical AND is only zeros.
Dependencies are inferred from the claim text.