Synchronization and channel deskewing circuitry for multi-channel serial links

A method of using first-in-first-out buffers on an integrated circuit to synchronize and deskew data received from multiple serial data streams, comprising:

• dynamically partitioning at least a given one of the first-in-first-out buffers into a deskew space and a synchronization space by writing the data from the serial data stream associated with that given first-in-first-out buffer into one or more slots in the given first-in-first-out buffer while all remaining slots in the given first-in-first-out buffer are allocated to the synchronization space;
• dynamically partitioning the synchronization space between underflow space and overflow space;
• deskewing and synchronizing the data from the multiple serial data streams using only a single write pointer for each of the serial data streams to write data into the first-in-first-out buffer circuitry and using only a single read pointer for each of the serial data streams to read data from the first-in-first-out buffer circuitry;
• decoding the multiple serial streams with 8B/10B decoder circuitry that receives the deskewed and synchronized versions of the multiple serial data streams from the first-in-first-out buffers, wherein the integrated circuit comprises programmable logic;
• and
• providing the deskewed, synchronized, and decoded data from the multiple serial data streams to the programmable logic on the integrated circuit.

A set of circuits on an integrated circuit for synchronizing and deskewing multiple serial data streams, comprising:

• a plurality of first-in-first-out buffers, each first-in-first-out buffer being associated with a respective one of the multiple serial data streams;
• 8B/10B decoder circuitry that receives the synchronized and deskewed versions of the multiple serial data streams from the first-in-first-out buffers, wherein the integrated circuit comprises a programmable logic device;
• and
• control circuitry that controls the first-in-first-out buffers so that each first-in-first-out buffer performs both synchronization and deskewing operations on its respective serial data stream, wherein the control circuitry is configured to:
• dynamically partition at least a given one of the first-in-first-out buffers into a deskew space and a synchronization space by writing the data from the serial data stream associated with that given first-in-first-out buffer into one or more slots in the given first-in-first-out buffer while all remaining slots in the given first-in-first-out buffer are allocated to the synchronization space;
• and
• dynamically partition the synchronization space between underflow space and overflow space.

A set of circuits in which serial data is communicated over a plurality of serial data links, comprising:

• a first integrated circuit having:
• circuitry for generating digital signals;
• a plurality of serializers for serializing the digital signals and providing a corresponding plurality of serial data streams;
• and
• a plurality of corresponding differential output buffers connected to the serializers that transmit the serial data streams;
• a second integrated circuit having:
• a plurality of differential input buffers that receive the transmitted serial data streams;
• a plurality of clock and data recovery circuits, each connected to a respective one of the differential input buffers for receiving a respective one of the serial data streams and for providing corresponding recovered data from the serial data streams and recovered clock signals from the serial data streams;
• a plurality of word-alignment circuits, each of which receives the recovered data and recovered clock signals from a respective one of the clock and data recovery circuits and that provides a corresponding word-aligned data signal;
• a plurality of first-in-first-out buffers that receive the recovered clock signals, wherein each of the first-in-first-out buffers receives the word-aligned data signal from a respective one of the word-alignment circuits and provides a corresponding data output signal and wherein the data output signals from the first-in-first-out buffers are synchronized and deskewed versions of the multiple serial data streams;
• 8B/10B decoder circuitry that receives the synchronized and deskewed versions of the multiple serial data streams from the first-in-first-out buffers, wherein the second integrated circuit comprises a programmable logic device;
• and
• control circuitry that controls the first-in-first-out buffers so that each first-in-first-out buffer performs both synchronization and deskewing operations on its respective word-aligned data signal, wherein the control circuitry is configured to:
• dynamically partition at least a given one of the first-in-first-out buffers into a deskew space and a synchronization space by writing data into one or more slots in the given first-in-first-out buffer while all remaining slots in the given first-in-first-out buffer are allocated to the synchronization space;
• and
• dynamically partition the synchronization space between underflow space and overflow space.