US 7,454,450 B2Granted

Mixed-signal system for performing Taylor series function approximations

AssigneeBoard of Regents, The University of Texas System

InventorsBrian Remy, Michael D. Bryant, Benito R. Fernandez, Shouli Yan

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Abstract

A mixed-signal system for performing Taylor series function approximations is disclosed. The mixed-signal system includes a digital-to-analog converter (DAC), multiple resistor-to-resistor (R2R) ladders, various digital registers, a digital processor and an analog integrator. The digital processor calculates coefficients F, Fx, Fy, Fxx, Fxy, Fyy of a Taylor series equation and calculates distance functions. The digital processor also includes a digital register for storing a magnitude scaling factor φ(x0,y0) of the Taylor series equation. The DAC control register uploads a lead term F(x0,y0) of the Taylor series equation from the digital processor to the DAC. The first-order digital registers controls resistances of the R2R ladders. The second-order digital registers uploads coefficients Fx, Fy, Fxx, Fxy, Fyy of the Taylor series equation from the digital processor to the DAC. The analog integrator adds outputs from the DAC and the R2R ladder to generate approximation results for the Taylor series equation.

Claims7

Dependent claims

A mixed-signal system for performing Taylor series approximations, said system comprising:

a digital processor for calculating coefficients Fx, Fy, Fxx, Fxy, Fyy of a Taylor series equation and for calculating distance functions, wherein said digital processor includes a digital register for storing a magnitude scaling factor φ(x0,y0) of said Taylor series equation;
a digital-to-analog converter (DAC) coupled to said digital processor;
a DAC control register, coupled to said DAC, for uploading a lead term F(x0,y0) of said Taylor series equation from said digital processor to said DAC;
a plurality of resistor-to-resistor (R2R) ladders coupled to said DAC;
a plurality of first-order digital registers, coupled to said R2R ladders, for controlling resistances of said R2R ladders;
a plurality of second-order digital registers, coupled to said digital processor, for uploading coefficients Fxx, Fxy, Fyy of said Taylor series equation from said digital processor to said DAC;
and
an analog integrator or operational amplifier for adding outputs from said DAC and said R2R ladder to generate approximation results for said Taylor series equation.

5 more elements

Dependencies are inferred from the claim text.