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OwnerJames Andrew Garrard Seawright, Ramesh Sathianathan +5inventors
InventorsJames Andrew Garrard Seawright, Ramesh Sathianathan, Christophe G. Gauthron, Jeremy R. Levitt, Kalyana C. Mulam, Chian-Min Richard Ho, Ping Fai Yeung
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A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.
A method of formal analysis of a description of a device, the method being implemented in a programmed computer, the method comprising:
An apparatus configured to provide formal analysis of a description of a device, the apparatus comprising:
Dependencies are inferred from the claim text.