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US 7,454,306 B2Granted
Frequency margin testing
AssigneeSilicon Laboratories Inc.
InventorJerrell P. Hein
Life of this patent
Estimating the term…
Abstract
A technique for performing frequency margin testing of communications system circuit boards incorporates a frequency agile clock source on a communications system circuit board. The clock source may be programmed to operate the circuit board at a nominal operating frequency and at frequencies suitable to characterize actual and/or apparent frequency tolerances of the circuit board. The technique maintains transmission line integrity of the on-board clock.
Claims17
An apparatus comprising:
- a circuit board;
- a frequency agile clock source comprising a substantially fixed frequency oscillator and a programmable oscillator coupled to the substantially fixed frequency oscillator, the frequency agile clock source supplying an operational clock signal to one or more circuits on the circuit board;
- and
- wherein the frequency agile clock source is programmable to adjust a frequency of the operational clock signal to determine a frequency tolerance of the circuit board,
- wherein the frequency of the operational clock signal is programmable above and below a nominal operating frequency of the circuit board sufficient to determine the frequency tolerance of the circuit board,
- wherein the frequency of the operational clock signal is programmable to be a frequency at least approximately ten percent higher than and is programmable to be a frequency at least approximately ten percent lower than the nominal operating frequency of the circuit board.
3 more elements
A method comprising:
- providing an operational clock signal to at least one circuit on a circuit board, the operational clock signal being based on a substantially fixed frequency signal provided by an oscillator on the circuit board and having a programmable frequency;
- and
- varying the operational clock signal to determine a frequency tolerance of the circuit board based on the operational clock signal,
- wherein the frequency of the operational clock signal is programmable in increments of approximately 10 ppm or less of a nominal operating frequency of the circuit board.
1 more element
Dependencies are inferred from the claim text.