US 7,454,303 B2 · System and method for compensating for PVT variation effects on the delay line of a clock signal

Abstract

The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

Claims21

Dependent claims

A method for process, voltage, and temperature compensation, comprising:

training at least one functional delay cell for a clock path which has a delay setting and training a spare delay cell which has a one-fourth cycle delay setting;
calculating a ratio for the at least one functional delay cell by dividing the at least one functional delay cells' delay setting into the spare delay cells' one-fourth cycle delay setting;
entering a functional mode and switching to a Master-Slave approach.

Dependencies are inferred from the claim text.

System and method for compensating for PVT variation effects on the delay line of a clock signal

Life of this patent

System and method for compensating for PVT variation effects on the delay line of a clock signal

Life of this patent

Abstract

Claims21