Method and apparatus for predicting system noise

A jitter calculator engine for estimating system jitter within a circuit design, comprising:

• a core effects module estimating core jitter caused by noise effects impacting a core clock network;
• an input/output (I/O) module estimating I/O input pin switching effects on a clock network input signal, the I/O module identifying a relative frequency of switching by I/O pins into the circuit design;
• and
• a phase lock loop (PLL) module for estimating an effect of a PLL on a signal delivered to the PLL from an I/O pin, the PLL module accounting for I/O input pin switching effects and core jitter.

A computer readable medium having program instructions for calculating system jitter in an integrated circuit design, comprising:

• program instructions for identifying operating parameters associated with the integrated circuit design;
• program instructions for evaluating interaction between Input/Output (I/O) pins based on placement of the I/O pins in the integrated circuit design;
• program instructions for determining an effect of the interaction between Input/Output (I/O) pins on the system jitter;
• program instructions for evaluating an impact of a phase lock loop (PLL) to jitter of an incoming signal to the PLL;
• and
• program instructions for combining the impact of the PLL to jitter of the incoming signal and the effect of the interaction between Input/Output (I/O) pins to derive the system jitter.