Information processing unit

An information processing unit comprising:

• an arithmetic unit;
• a memory device for storing data transmitted from the arithmetic unit;
• a data bus, the number of bits of which is (N+r), said data bus connecting the arithmetic unit to the memory device;
• a random number generator;
• and
• a data transform device,
• wherein:
• using, as a key, data formed of a random number having a length of r bits generated by the random number generator, said data transform device encrypts data having a length of N bits, which has been transmitted from the arithmetic unit, to generate encrypted data having a length of N bits, and then concatenates the encrypted data with the random number to generate data having a length of (N+r) bits before outputting the data having a length of (N+r) bits to the data bus.

An information processing unit comprising:

• an arithmetic unit;
• a memory device for storing data transmitted from the arithmetic unit;
• a data bus, the number of bits of which is (N+r), said data bus connecting the arithmetic unit to the memory device;
• a random number generator;
• and
• a data transform device,
• wherein:
• said data transform device concatenates data having a length of N bits transmitted from the arithmetic unit with a random number having a length of r bits generated by the random number generator, and thereby generates data having a length of (N+r) bits, and then performs nonlinear transformation of the data having a length of (N+r) bits before outputting the transformed data to the data bus.

An information processing unit comprising:

• an arithmetic unit;
• a memory device for storing data transmitted from the arithmetic unit;
• a data bus, the number of bits of which is N, said data bus connecting the arithmetic unit to the memory device;
• a random number generator;
• and
• a data transform device,
• wherein:
• said data transform device receives, as input, data having a length of N bits, and then outputs to the data bus an inverse element having a length of N bits in which irreducible polynomial m(x) in GF(2n) is a value of modulo.

An information processing unit comprising:

• an arithmetic unit;
• a memory device for storing data transmitted from the arithmetic unit;
• a data bus, the number of bits of which is (N+r), said data bus connecting the arithmetic unit to the memory device;
• an ECC generator for generating an ECC having a length of r bits from data having a length of N bits received from the arithmetic unit;
• a random number generator;
• and
• a data transform device,
• wherein:
• by use of a random number generated by the random number generator, said data transform device determines at random a bus line of the data bus, through which the data having a length of N bits received from the arithmetic unit and the ECC having a length of r bits generated by the ECC generator are transmitted to the memory device.