Sampling-error phase compensating apparatus and method thereof

An apparatus for compensating a sampling phase error of a received signal, the apparatus comprising:

• a phase detector to receive the received signal and a sampling clock signal, and thereby output a plurality of phase detection signals, wherein each of the phase detection signals corresponds to a phase state and a phase error between the received signal and the sampling clock signal;
• a first phase regulating unit, coupled to the phase detector, to output a first phase regulating signal according to the phase detection signals for fine regulation when an absolute value of the phase detection signal, indicating the phase error, is not larger than a first threshold value,
• wherein in response to a first number of the phase detection signals continuously representing a phase leading state, the first phase regulating unit outputs the first phase regulating signal which includes at least one phase backward regulating signal and at least a phase non-backward regulating signal in order to prevent over-adjustment of the sampling clock signal, and
• in response to a second number of the phase detection signals continuously representing a phase lagging state, the first phase regulating unit outputs the first phase regulating signal which includes at least one phase forward regulating signal and at least a phase non-forward regulating signal in order to prevent over-adjustment of the sampling clock signal;
• and a phase adjusting unit, coupled between the phase detector and the first phase regulating unit, to adjust the sampling clock signal according to the first phase regulating signal for the fine regulation;
• wherein the first number of phase detection signals and the second number of phase detection signals depend on a delay time from detection of a phase error between the received signal and the sampling clock signal to adjustment of the sampling clock signal for the phase error in the apparatus.

An apparatus for compensating a sampling phase error of a received signal, the apparatus comprising:

• a phase detector to receive the received signal and a sampling clock signal, and thereby output a plurality of phase detection signals, wherein each of the phase detection signals corresponds to a phase state and a phase error between the received signal and the sampling clock signal;
• a second phase regulating unit to output a second phase regulating signal according to the phase detection signals for coarse regulation;
• a fine phase regulating unit to output a fine phase regulating signal according to the phase detection signals for fine regulation,
• wherein in response to a first number of the phase detection signals continuously representing a phase leading state, the first phase regulating unit outputs the first phase regulating signal which includes at least one phase backward regulating signal and at least a phase non-backward regulating signal in order to prevent over-adjustment of the sampling clock signal;
• and
• wherein in response to a second number of the phase detection signals continuously representing a phase lagging state, the first phase regulating unit outputs the first phase regulating signal which includes at least one phase forward regulating signal and at least a phase non-forward regulating signal in order to prevent over-adjustment of the sampling clock signal;
• a digital loop filter, coupled to the first phase regulating unit, to count the first phase regulating signal to obtain a counter value, and to generate the first phase regulating signal when the counter value is not smaller than a specific threshold value;
• and
• a phase adjusting unit, coupled to the first phase regulating unit and the second phase regulating unit, to adjust the sampling clock signal according to the second phase regulating signal and the phase regulating signal;
• wherein the first number of phase detection signals and the second number of phase detection signals depend on a delay time from detection of a phase error between the received signal and the sampling clock signal to adjustment of the sampling clock signal for the phase error in the apparatus, and the first number of phase detection signals and the second number of phase detection signals are not larger than the specific threshold value of the digital loop filter.