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US 7,453,970 B2Granted
Clock signal selecting apparatus and method that guarantee continuity of output clock signal
AssigneeElectronics and Telecommunications Research Institute
InventorsTae Sik Cheung, Bhum Cheol Lee, Bong Tae Kim
Life of this patent
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Abstract
Provided are a clock signal selecting apparatus and method that can guarantee the continuity of an output clock signal. The clock signal selecting apparatus and method can synchronize the phases of at least two clock signals by continuously controlling the phases of the clock signals. Accordingly, even when an active clock signal and a standby clock signal have different frequencies, it is possible to guarantee the continuity of the output clock signal regardless of whether the clock signals are switched from one to another. In addition, it is possible to guarantee the stability of the output clock signal.
Claims24
A clock signal selecting apparatus that guarantees the continuity of an output clock signal, the clock signal selecting apparatus comprising:
- N phase comparators, each of which compares the phase of one of N phase-controlled clock signals with the phase of a second one of said N phase controlled clock signals, which is an active clock signal, and generates one of N control signals that control the phase of one of N clock signals to follow the phase of a predetermined clock signal;
- N phase controllers, which control the phases of the N clock signals in response to the N control signals and generate the N phase-controlled clock signals;
- and
- a selector, which selects one of the N phase-controlled clock signals corresponding to the active clock signal,
- wherein if each of the N phase-controlled clock signals corresponds to the active clock signal, each of the N phase controllers generates a phase-controlled clock signal having a constant phase difference with an input clock signal, and N is an integer greater than one.
2 more elements
A clock signal selecting apparatus that guarantees the continuity of an output clock signal, the clock signal selecting apparatus comprising:
- a first phase comparator, which compares first and second phase-controlled clock signals with each other and generates a first control signal that controls the phase of the first phase-controlled clock signal to follow the phase of the second phase-controlled clock signal;
- a second phase comparator, which compares the first and second phase-controlled clock signals with each other and generates a second control signal that controls the phase of the second phase-controlled clock signal to follow the phase of the first phase-controlled clock signal;
- a first phase controller, which generates the first phase-controlled clock signal by controlling the phase of a first clock signal and controls the phase of the first phase-controlled clock signal in response to the first control signal;
- a second phase controller, which generates the second phase-controlled clock signal by controlling the phase of a second clock signal and controls the phase of the second phase-controlled clock signal in response to the second control signal;
- and
- a selector, which selects one of the first and second phase-controlled clock signals output from the first and second phase controllers, respectively,
- wherein if the first clock signal is designated as an active clock signal, the first phase controller controls the phase of the first phase-controlled clock signal to have a constant difference with respect to the phase of the first clock signal, and
- wherein if the second clock signal is designated as the active clock signal, the second phase controller controls the phase of the second phase-controlled clock signal to have a constant difference with respect to the phase of the second clock signal.
5 more elements
A clock signal selecting apparatus that guarantees the continuity of an output clock signal, the clock signal selecting apparatus comprising:
- a first multi-phase clock signal generator, which converts a first clock signal into a plurality of first multi-phase clock signals;
- a second multi-phase clock signal generator, which converts a second clock signal into a plurality of second multi-phase clock signals;
- a first phase comparator/controller, which compares the phases of the first multi-phase clock signals with the phase of a second phase-controlled clock signal and generates a first phase-controlled clock signal by controlling the phase of the first clock signal based on comparison results, the second phase-controlled clock signal being obtained by controlling the phase of the second clock signal;
- a second phase comparator/controller, which compares the phases of the second multi-phase clock signals with the phase of the first phase-controlled clock signal, generates the second phase-controlled clock signal by controlling the phase of the second clock signal based on comparison results, and outputs the second phase-controlled clock signal to the first phase comparator/controller;
- and
- a selector, which outputs one of the first and second phase-controlled clock signals in response to a clock selection signal input from the outside of the clock signal selecting apparatus.
3 more elements
A clock signal selecting method that guarantees the continuity of an output clock signal, the clock signal selecting method comprising:
- (a) comparing the phase of one of N phase-controlled clock signals with the phase of a second N phase-controlled clock signal which is an active clock signal;
- (b) generating a control signal that controls the phase of each of N clock signals to follow the phase of a predetermined clock signal;
- (c) generating the N phase-controlled clock signals by controlling the phases of the N clock signals in response to the control signal;
- and
- (d) selecting one of the N phase-controlled clock signals corresponding to the active clock signal,
- wherein if each of the N phase-controlled clock signals corresponds to the active clock signal, each of the N phase controllers generates a phase-controlled clock signal having a constant phase difference with an input clock signal, and N is an integer greater than one.
3 more elements
A clock signal selecting method that guarantees the continuity of an output clock signal, the clock signal selecting method comprising:
- (a) comparing first and second phase-controlled clock signals, which are obtained by controlling the phases of first and second clock signals, with each other and generating a first control signal that controls the phase of the first phase-controlled clock signal to follow the phase of the second phase-controlled clock signal;
- (b) comparing the first and second phase-controlled clock signals with each other and generating a second control signal that controls the phase of the second phase-controlled clock signal to follow the phase of the first phase-controlled clock signal;
- (c) controlling the phase of the first phase-controlled clock signal in response to the first control signal;
- (d) controlling the phase of the second phase-controlled clock signal in response to the second control signal;
- and
- (e) selecting one of the first and second phase-controlled clock signals whose phases are controlled in (c) and (d), respectively, wherein (c) comprises:
- (c-1) controlling the phase of the first phase-controlled clock signal to have a constant difference with the phase of the first clock signal if the first clock signal is an active clock signal;
- and
- (c-2) controlling the phase of the first phase-controlled clock signal to be in synchronization with the phase of the second phase-controlled clock signal within a predetermined error range in response to the first control signal, if the first clock signal is a standby clock signal.
6 more elements
A clock signal selecting method that guarantees the continuity of an output clock signal, the clock signal selecting method comprising:
- (a) comparing first and second phase-controlled clock signals, which are obtained by controlling the phases of first and second clock signals, with each other and generating a first control signal that controls the phase of the first phase-controlled clock signal to follow the phase of the second phase-controlled clock signal:
- (b) comparing the first and second phase-controlled clock signals with each other and generating a second control signal that controls the phase of the second phase-controlled clock signal to follow the phase of the first phase-controlled clock signal:
- (c) controlling the phase of the first phase-controlled clock signal in response to the first control signal:
- (d) controlling the phase of the second phase-controlled clock signal in response to the second control signal;
- and
- (e) selecting one of the first and second phase-controlled clock signals whose phases are controlled in (c) and (d), respectively, wherein (d) comprises:
- (d-1) controlling the phase of the second phase-controlled clock signal to have a constant difference with the phase of the second clock signal if the second clock signal is the active clock signal;
- and
- (d-2) controlling the phase of the second phase-controlled clock signal to be in synchronization with the phase of the first phase-controlled clock signal within a predetermined error range in response to the second control signal, if the second clock signal is designated as the standby clock signal.
6 more elements
A clock signal selecting method that guarantees the continuity of an output clock signal, the clock signal selecting method comprising:
- (a) converting a first clock signal into a plurality of first multi-phase clock signals, and converting a second clock signal into a plurality of second multi-phase clock signals;
- (b) comparing the phases of the first multi-phase clock signals with the phase of a second phase-controlled clock signal and selecting at least two of the first multi-phase clock signals having almost the same phase as the second phase-controlled clock signal;
- (c) comparing the phases of the second multi-phase clock signals with the phase of a first phase-controlled clock signal and selecting at least two of the second multi-phase clock signals having almost the same phase as the first phase-controlled clock signal;
- (d) if the first clock signal is an active clock signal, generating the first phase-controlled clock signal having a constant phase difference with the first clock signal and generating the second phase-controlled clock signal by combining the second multi-phase clock signals selected in (c) together;
- (e) if the second clock signal is the active signal , generating the first phase-controlled clock signal having a constant phase difference with the second clock signal and generating the first phase-controlled clock signal by combining the first multi-phase clock signals selected in (b) together;
- and
- (f) outputting one of the first or second clock signals, which is designated as the active clock signal, as an output clock signal.
4 more elements
Dependencies are inferred from the claim text.