Dynamic phase alignment methods and apparatus
AssigneeAltera Corporation
InventorsRichard Yen-Hsiang Chang, Gregory Starr
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Abstract
Dynamic phase alignment circuitry selects from among several, phase-distributed, candidate clock signals the one of those signals that is currently best for use in controlling the timing of sampling of a serial data signal to recover the data from that signal. The circuitry selects two phase-adjacent ones of the candidate clock signals that are currently the two best candidates for final selection. The circuitry makes a final selection of the generally better one of these two best candidates in a way that avoids unproductive switching back and forth between these two best candidates.
Claims32
Dynamic phase alignment circuitry comprising:
- a source of a plurality of phase-distributed clock signals;
- circuitry for selecting two, phase-adjacent ones of the clock signals that currently have transitions on respective opposite sides of transitions in a serial data signal, the circuitry separately monitoring the consistency with which each of the selected two, phase-adjacent clock signals has transitions on each side of the transitions in the serial data signal and further selecting one of the selected two clock signals based on the consistency;
- and
- output circuitry for outputting the further selected one clock signal for use as a basis for selecting sampling times of the serial data signal to recover data therefrom, wherein the circuitry for selecting makes no change in its clock signal selections unless a consistency measure threshold is reached for one of the selected two clock signals.
A method for dynamic phase alignment comprising:
- selecting two phase-adjacent ones of a plurality of phase-distributed clock signals;
- comparing phases of the selected two phase-adjacent clock signals to phase of a serial data signal;
- and
- changing the selected phase-adjacent clock signals until the phases of the selected two phase-adjacent clock signals are predominantly on respective opposite sides of the phase of the serial data signal, and thereafter changing the selected phase-adjacent clock signals only if a first of those signals becomes more predominantly on one side of the phase of the serial data signal than a second of those signals by a predetermined amount.
Dynamic phase alignment circuitry comprising:
- circuitry for controllably selecting two phase-adjacent ones of a plurality of phase-distributed clock signals;
- circuitry for comparing phases of the selected two phase-adjacent clock signals to phase of a serial data signal;
- and
- circuitry responsive to the circuitry for comparing for controlling the circuitry for controllably selecting to change the selected phase-adjacent clock signals until the phases of the selected two phase-adjacent clock signals are predominantly on respective opposite sides of the phase of the serial data signal, and to thereafter change the selected phase-adjacent clock signals only if a first of those signals becomes more predominantly on one side of the phase of the serial data signal than a second of those signals by a predetermined amount.
Dependencies are inferred from the claim text.