Method and device for extracting a clock frequency underlying a data stream

A method for extracting a clock frequency underlying a data stream, wherein the data stream comprises a first data pattern, in regular first temporal intervals specified with a relative first accuracy, and wherein the data stream further comprises a second data pattern comprising a plurality of clock periods with the clock frequency or a multiple of the clock frequency, wherein the clock periods are specified with a second relative accuracy which is smaller than the first relative accuracy, comprising:

• controlling a controllable oscillator for providing an oscillator clock with an oscillator clock frequency using a coarse-tuning step, a fine-tuning step and a frequency-tracking step, wherein controlling is performed by means of a first digital/analog converter and a second digital/analog converter and a summer coupled to the outputs of the first digital/analog converter and the second digital/analog converter and is implemented to provide a control signal for the controllable oscillator,
• wherein in the coarse-tuning step using the second data pattern and a number of clock periods of the oscillator the oscillator clock frequency is decreased or increased;
• and
• wherein in the fine-tuning step following the coarse-tuning step using a first data pattern and a temporally subsequent first data pattern and a number of clock periods of the oscillator between the first data pattern and the temporally subsequent first data pattern the oscillator clock frequency is decreased or increased,
• whereby the oscillator clock frequency with the relative second accuracy is obtained which is equal to the clock frequency underlying the data stream or to a multiple or a fraction of the clock frequency underlying the data stream,
• wherein by the coarse-tuning step and the fine-tuning step bits of the first digital/analog converter are set, and
• wherein the frequency-tracking step is performed after the coarse-tuning step and after the fine-tuning step, and wherein in the frequency-tracking step bits of the second digital/analog converter are set.

A device for extracting a clock frequency underlying a data stream, wherein the data stream comprises a first data pattern in regular first temporal intervals specified with a relative first accuracy, and wherein the data stream further comprises a second data pattern comprising a plurality of clock periods with the clock frequency or a multiple of the clock frequency, wherein the clock periods are specified with a second relative accuracy smaller than the first relative accuracy, comprising:

• a controller for controlling a controllable oscillator for providing an oscillator clock with an oscillator clock frequency;
• a coarse-tuner implemented
• to control the controller for controlling the controllable oscillator in order to decrease the oscillator clock frequency of the controllable oscillator or in order to increase the oscillator clock frequency, using the second data pattern and a number of clock periods of the oscillator;
• and
• a fine-tuner which is operable after the coarse-tuner was operable and which is implemented
• to control the controller for controlling the controllable oscillator in order to decrease the oscillator clock frequency of the controllable oscillator or to increase the oscillator clock frequency of the controllable oscillator, using a first data pattern and a temporally subsequent first data pattern and a number of clock periods of the oscillator between the first data pattern and the temporally subsequent first data pattern,
• whereby the oscillator clock frequency with the relative second accuracy is obtained equal to the clock frequency underlying the data stream or equal to a multiple or a fraction of the clock frequency underlying the data stream,
• wherein the oscillator control comprises a digital/analog converter,
• wherein the digital/analog converter is supplied with a binary number of a width of n bits on the input side, wherein a control quantity supplied by the digital/analog converter on the output side is supplied to the controllable oscillator,
• wherein the coarse-tuner is implemented in order to determine, iteratively and based on a most significant bit, a predetermined number of low-order bits following the most significant bit, wherein the predetermined number is smaller than n, and
• wherein the fine-tuner is implemented in order to determine, iteratively and based on a bit whose order is smaller than a least significant bit determined by the coarse-tuning means, remaining bits of the digital/analog converter.

A method for extracting a clock frequency underlying a data stream, wherein the data stream comprises a first data pattern, in regular first temporal intervals specified with a relative first accuracy, and wherein the data stream further comprises a second data pattern comprising a plurality of clock periods with the clock frequency or a multiple of the clock frequency, wherein the clock periods are specified with a second relative accuracy which is smaller than the first relative accuracy, comprising:

• controlling a controllable oscillator for providing an oscillator clock with an oscillator clock frequency using a coarse-tuning step and a fine-tuning step,
• wherein the coarse-tuning step is implemented to decrease or increase the oscillator clock frequency using the second data pattern and a number of clock periods of the oscillator;
• and
• wherein the fine-tuning step following the coarse-tuning step is implemented in order to decrease or increase the oscillator clock frequency using a first data pattern and a temporally subsequent first data pattern and a number of clock periods of the oscillator between the first data pattern and the temporally subsequent first data pattern,
• whereby the oscillator clock frequency with the relative second accuracy is obtained which is equal to the clock frequency underlying the data stream or equal to a multiple or to a fraction of the clock frequency underlying the data stream,
• wherein for an oscillator control a digital/analog converter is present, wherein the digital/analog converter is supplied on the input side with a binary number of a width of n bits, wherein a control quantity provided by the digital/analog converter on the output side is supplied to the controllable oscillator,
• wherein in the coarse-tuning step, iteratively and based on a most significant bit, a predetermined number of low-order bits following the most significant bits is determined, wherein the predetermined number is smaller than n, and
• wherein in the fine-tuning step, iteratively and based on a bit whose order is smaller than a least significant bit determined by the coarse-tuning means, remaining bits of the digital/analog converter are determined.

A computer program stored on a computer readable medium for performing a method for extracting a clock frequency underlying a data stream, wherein the data stream comprises a first data pattern, in regular first temporal intervals specified with a relative first accuracy, and wherein the data stream further comprises a second data pattern comprising a plurality of clock periods with the clock frequency or a multiple of the clock frequency, wherein the clock periods are specified with a second relative accuracy which is smaller than the first relative accuracy, comprising:

• controlling a controllable oscillator for providing an oscillator clock with an oscillator clock frequency using a coarse-tuning step, a fine-tuning step and a frequency-tracking step, wherein controlling is performed by means of a first digital/analog converter and a second digital/analog converter and a summer coupled to the outputs of the first digital/analog converter and the second digital/analog converter and is implemented to provide a control signal for the controllable oscillator,
• wherein in the coarse-tuning step using the second data pattern and a number of clock periods of the oscillator the oscillator clock frequency is decreased or increased;
• and
• wherein in the fine-tuning step following the coarse-tuning step using a first data pattern and a temporally subsequent first data pattern and a number of clock periods of the oscillator between the first data pattern and the temporally subsequent first data pattern the oscillator clock frequency is decreased or increased,
• whereby the oscillator clock frequency with the relative second accuracy is obtained which is equal to the clock frequency underlying the data stream or to a multiple or a fraction of the clock frequency underlying the data stream,
• wherein by the coarse-tuning step and the fine-tuning step bits of the first digital/analog converter are set, and
• wherein the frequency-tracking step is performed after the coarse-tuning step and after the fine-tuning step, and wherein in the frequency-tracking step bits of the second digital/analog converter are set
• when the computer program runs on a computer.

A computer program comprising stored on a computer readable medium for performing a method for extracting a clock frequency underlying a data stream, wherein the data stream comprises a first data pattern, in regular first temporal intervals specified with a relative first accuracy, and wherein the data stream further comprises a second data pattern comprising a plurality of clock periods with the clock frequency or a multiple of the clock frequency, wherein the clock periods are specified with a second relative accuracy which is smaller than the first relative accuracy, comprising:

• controlling a controllable oscillator for providing an oscillator clock with an oscillator clock frequency using a coarse-tuning step and a fine-tuning step,
• wherein the coarse-tuning step is implemented to decrease or increase the oscillator clock frequency using the second data pattern and a number of clock periods of the oscillator;
• and
• wherein the fine-tuning step following the coarse-tuning step is implemented in order to decrease or increase the oscillator clock frequency using a first data pattern and a temporally subsequent first data pattern and a number of clock periods of the oscillator between the first data pattern and the temporally subsequent first data pattern,
• whereby the oscillator clock frequency with the relative second accuracy is obtained which is equal to the clock frequency underlying the data stream or equal to a multiple or to a fraction of the clock frequency underlying the data stream,
• wherein for an oscillator control a digital/analog converter is present, wherein the digital/analog converter is supplied on the input side with a binary number of a width of n bits, wherein a control quantity provided by the digital/analog converter on the output side is supplied to the controllable oscillator,
• wherein in the coarse-tuning step, iteratively and based on a most significant bit, a predetermined number of low-order bits following the most significant bits is determined, wherein the predetermined number is smaller than n, and
• wherein in the fine-tuning step, iteratively and based on a bit whose order is smaller than a least significant bit determined by the coarse-tuning means, remaining bits of the digital/analog converter are determined,
• when the computer program runs on a computer.

A device for extracting a clock frequency underlying a data stream, wherein the data stream comprises a first data pattern at regular first temporal intervals specified with a relative first accuracy, and wherein the data stream further comprises a second data pattern comprising a plurality of clock periods with the clock frequency or a multiple of the clock frequency, wherein the clock periods are specified with a second relative accuracy smaller than the first relative accuracy, comprising:

• control means for controlling a controllable oscillating means for providing an oscillator clock with an oscillator clock frequency, wherein the control means for controlling comprises both a first digital/analog converting means and a second digital/analog converting means and a summer, coupled to the outputs of the first digital/analog converting means and the second digital/analog converting means and implemented in order to provide a control signal for the controllable oscillating means;
• a coarse tuning means implemented in order to control the control means for controlling the oscillating means using the second data pattern and a number of clock periods of the oscillating means in order to reduce the oscillator clock frequency of the controllable oscillator or to increase the oscillator clock frequency;
• a fine tuning means operable after the coarse tuning means was operable and implemented in order to control the control means for controlling the oscillating means using the first data pattern and a temporally subsequent first data pattern and a number of clock periods of the oscillating means between the first data pattern and the temporally subsequent first data pattern in order to reduce the oscillating means clock frequency of the controllable oscillating means or to increase the oscillating means clock frequency of the controllable oscillating means,
• whereby the clock frequency of the controllable oscillating means is obtained with the relative second accuracy which is equal to the clock frequency underlying the data stream or equal to a multiple or a fraction of the clock frequency underlying the data stream,
• wherein the coarse tuning means and the fine tuning means are operable in order to set bits of the first digital/analog converting means;
• and
• a frequency-tracking means which is implemented in order to be operable after a coarse tuning by the coarse tuning means and after a fine tuning by the fine-tuning means in order to set bits of the second digital/analog converting means.

A device for extracting a clock frequency underlying a data stream, wherein the data stream comprises a first data pattern in regular first temporal intervals specified with a relative first accuracy, and wherein the data stream further comprises a second data pattern comprising a plurality of clock periods with the clock frequency or a multiple of the clock frequency, wherein the clock periods are specified with a second relative accuracy smaller than the first relative accuracy, comprising:

• a control means for controlling a controllable oscillating means for providing an oscillator clock with an oscillator clock frequency;
• a coarse tuning means implemented
• to control the control means for controlling the controllable oscillating means in order to decrease the oscillator clock frequency of the controllable oscillator or in order to increase the oscillator clock frequency, using the second data pattern and a number of clock periods of the oscillating means;
• and
• a fine tuning means which is operable after the coarse tuning means was operable and which is implemented
• to control the control means for controlling the controllable oscillating means in order to decrease the oscillator clock frequency of the controllable oscillator or to increase the oscillator clock frequency of the controllable oscillator, using a first data pattern and a temporally subsequent first data pattern and a number of clock periods of the oscillating means between the first data pattern and the temporally subsequent first data pattern,
• whereby the oscillator clock frequency with the relative second accuracy is obtained equal to the clock frequency underlying the data stream or equal to a multiple or a fraction of the clock frequency underlying the data stream,
• wherein the controllable oscillating means comprises a digital/analog converting means,
• wherein the digital/analog converting means is supplied with a binary number of a width of n bits on the input side, wherein a control quantity supplied by the digital/analog converting means on the output side is supplied to the controllable oscillating means,
• wherein the coarse tuning means is implemented in order to determine, iteratively and based on a most significant bit, a predetermined number of low-order bits following the most significant bit, wherein the predetermined number is smaller than n, and
• wherein the fine tuning means is implemented in order to determine, iteratively and based on a bit whose order is smaller than a least significant bit determined by the coarse-tuning means, remaining bits of the digital/analog converting means.