System and method for ordering of data transferred over multiple channels
AssigneeSilicon Graphics, Inc.
InventorsRandal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
Life of this patent
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Abstract
A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).
Claims14
A method for ordering data transferred over multiple channels, comprising:
- generating a first data packet in a particular packet flow in response to a first flow control credit;
- generating a first sequence number;
- inserting the first sequence number into the first data packet;
- selecting a first one of a plurality of channels to transfer the first data packet according to channel capacities of the plurality of channels;
- transferring the first data packet over the selected first one of the plurality of channels;
- generating a second data packet in the particular packet flow in response to a second flow control credit;
- generating a second sequence number;
- inserting the second sequence number into the second data packet;
- selecting a second one of a plurality of channels to transfer the second data packet according to channel capacities of the plurality of channels;
- transferring the second data packet of the particular packet flow over the selected second one of the plurality of channels, the second one of the plurality of channels being different than the first one of the plurality of channels as a result of varying channel capacities among the plurality of channels.
A system for ordering data transferred over multiple channels, comprising:
- a sequence number unit operable to generate a first sequence number;
- a request channel controller operable to receive a first data packet of a particular packet flow in response to a first flow control credit, the request channel controller operable to insert the first sequence number into the first data packet, the request channel controller operable to select a first one of a plurality of request channels according to channel capacities of the plurality of request channels, the request channel controller operable to transfer the first data packet over the selected first one of the plurality of request channels, the request channel controller operable to receive a second data packet in the particular packet flow in response to a second flow control credit, the request channel controller operable to insert a second sequence number into the second data packet, the request channel controller operable to select a second one of the plurality of request channels according to channel capacities of the plurality of request channels, the request channel controller operable to transfer the second data packet over the selected second one of the plurality of request channels, the second one of the plurality of channels being different than the first one of the plurality of channels as a result of varying channel capacities among the plurality of channels.
A system for ordering data transferred over multiple channels, comprising:
- a write port controller operable to receive a plurality of data packets of a particular packet flow in a non-sequential order over different ones of a plurality of channels, each data packet including a sequence number;
- a re-order buffer operable to store the plurality of data packets, the write port controller operable to place each data packet into the re-order buffer in response to its sequence number;
- a valid bit unit operable to generate a valid bit for each portion of the re-order buffer, the valid bit unit operable to set a valid bit for a corresponding portion of the re-order buffer in response to a data packet being stored therein;
- a read port controller operable to provide data packets in a sequential order in response to a valid bit being set.
Dependencies are inferred from the claim text.