Apparatus and method of controlling bank of semiconductor memory
AssigneeHynix Semiconductor Inc.
InventorSeung-Wook Kwack
Life of this patent
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Abstract
An apparatus for controlling bank of a semiconductor memory includes a plurality of banks, a peripheral circuit unit that generates and outputs a bank selection signal and a first address, and a bank controller that generates a second address obtained by correcting the first address to match a bank control timing and outputs the generated second address to a bank corresponding to the bank selection signal among the plurality of banks. Since it is easy to ensure a timing margin, it is possible to completely prevent an address generation error, minimize a layout area, and reduce current consumption.
Claims28
An apparatus for controlling a bank of a semiconductor memory apparatus, comprising:
- a plurality of banks;
- a peripheral circuit unit configured to generate and output a bank selection signal and a first address;
- and
- a bank controller configured to generate a second address by correcting the first address to match a bank control timing and output the generated second address to a bank corresponding to the bank selection signal among the plurality of banks.
An apparatus for controlling a bank of a semiconductor memory apparatus, comprising:
- a plurality of bank areas, each of which has a plurality of banks;
- a peripheral circuit unit configured to generate and output a bank selection signal and a first address;
- and
- a plurality of bank controllers, each of which is configured to generate a second address by correcting the first address to match a bank control timing and output the generated second address to a bank corresponding to the bank selection signal among the plurality of banks in each of the bank areas.
A method of controlling a bank of a semiconductor memory apparatus that includes a peripheral circuit unit configured to generate a bank selection signal and a first address, column controllers, and a bank controller, the method comprising:
- causing the bank controller to correct the first address to match a bank control timing according to the bank selection signal to generate a second address;
- causing the bank controller to output the second address according to the bank selection signal;
- and
- causing the column controllers to control the banks according to the second address.
Dependencies are inferred from the claim text.