Semiconductor memory device changing refresh interval depending on temperature
AssigneeFujitsu Limited
InventorsAkinobu Shirota, Kuninori Kawabata
Life of this patent
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Abstract
A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.
Claims13
A semiconductor memory device comprising:
- a memory core circuit having memory cells for storing data;
- a circuit configured to refresh said memory core circuit at a refresh interval;
- a temperature detecting unit configured to detect temperature;
- a control circuit configured to elongate the refresh interval in response to detection of a temperature drop by said temperature detecting unit after refreshing every one of the memory cells at least once following the detection of the temperature drop.
A memory system comprising:
- a unit configured to output a address;
- and
- a DRAM device configured to receive the address from the unit and configured to execute a refresh operation;
- wherein the DRAM device comprising:
- a memory core circuit having memory cells for storing data;
- a circuit configured to refresh said memory core circuit at a refresh interval;
- a temperature detecting unit configured to detect temperature;
- a control circuit configured to elongate the refresh interval in response to detection of a temperature drop by said temperature detecting unit after refreshing every one of the memory cells at least once following the detection of the temperature drop.
A semiconductor memory device comprising:
- a memory core circuit having memory cells for storing data;
- a circuit configured to refresh said memory core circuit at a refresh interval;
- a temperature detecting unit configured to detect temperature;
- and
- a control circuit configured to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by said temperature detecting unit,
- wherein said control circuit includes a counter circuit that starts counting when the drop is detected and elongates after reaching a predetermined count value.
A semiconductor memory device comprising:
- a memory core circuit having memory cells for storing data;
- a circuit configured to refresh said memory core circuit at a refresh interval;
- a temperature detecting unit configured to detect temperature;
- and
- a control circuit configured to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by said temperature detecting unit,
- wherein said control circuit includes a memory circuit that stores a refresh address when the drop is detected.
- wherein the control circuit elongates when a new refresh address is coincident with the refresh address in the memory circuit.
Dependencies are inferred from the claim text.