Semiconductor memory apparatus
AssigneeHynix Semiconductor Inc.
InventorJun-Hyun Chun
Life of this patent
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Abstract
A semiconductor memory apparatus which can restrict a refresh operation for a period when an internal clock is synchronized with an external clock. The semiconductor memory apparatus includes a refresh control unit that disables a refresh command signal which is applied during a period when an enable signal is enabled but a lock-completion signal is not enabled in response to the enable signal outputted from a mode register, the lock-completion signal outputted from a clock synchronizing unit, and the refresh command signal outputted from a command decoder. The clock synchronizing unit can stably complete a locking operation within a predetermined time regardless of power-supply noise and so on.
Claims11
A semiconductor memory apparatus comprising:
- a command decoder adapted to output a refresh command signal;
- a mode register-adapted to output an enable signal;
- a clock synchronizing unit adapted to output a lock completion signal;
- a refresh control unit coupled to the command decoder, the mode register and the clock synchronizing unit and adapted to disable the refresh command signal applied during a period when the enable signal is enabled but the lock-completion signal is not enabled, in response to the enable signal, the lock-completion signal, and the refresh command signal.
A semiconductor memory apparatus comprising:
- a command buffer adapted to receive an external command signal, convert the external command signal into an internal command signal having a level suitable for an internal circuit, and output the internal command signal;
- an address buffer adapted to receive an external address signal, convert the external address signal into an internal address signal having a level suitable for the internal circuit, and output the internal address signal;
- a command decoder coupled to the command buffer to receive the internal command signal and adapted to output a refresh command signal, a mode-register-set command signal, and an extended mode-register-set command signal;
- a mode register coupled to the command decoder to receive the mode-register-set command signal and the extended mode-register-set command signal and coupled to the address buffer to receive the internal address signal and adapted to output a mode register setting signal and an extended mode-register-setting signal including an enable signal;
- a clock synchronizing unit coupled to the mode register to receive and be driven by the enable signal, and is adapted to synchronize an internal clock signal with an external clock signal, and output a lock-completion signal and the synchronized internal clock signal when a locking operation is completed;
- and
- a refresh control unit adapted to receive the lock-completion signal outputted from the clock synchronizing unit, the enable signal outputted from the mode register, and the refresh command signal outputted from the command decoder and to disable the refresh command signal input during a period when the enable signal is enabled but the lock-completion signal is not enabled.
Dependencies are inferred from the claim text.