Method for hiding a refresh in a pseudo-static memory with plural DRAM sub-arrays and an on-board address decoder
AssigneePurple Mountain Server LLC
InventorKenneth J. Mobley
Life of this patent
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Abstract
A method and device for hiding refresh operations during accesses to sub-arrays of a pseudo-static memory device. By refreshing sub-arrayj while filling the row Ri (where i≠j) corresponding to sub-arrayi, refresh operations can be performed without risking that a read request will interrupt the refresh operation. Additional refresh operations of sub-arrayi can be performed serially with the operations of filling the row Ri without delaying the overall burst read or write operation if the burst is made sufficiently long.
Claims20
A memory device having plural DRAM sub-array groups, each DRAM sub-array group comprising plural DRAM sub-arrays, and each DRAM sub-array comprising plural array rows, comprising:
- an address decoder for decoding an address of a memory access request and indicating which of the plural DRAM sub-arrays are referenced by the memory access request;
- and
- refresh circuitry to perform a refresh contemporaneously with the memory access request of at least one array row of at least one of the plural DRAM sub-arrays not referenced by the memory access request, comprising a refresh counter and a missed refresh counter for each DRAM sub-array, wherein the refresh is performed by refreshing at least one DRAM sub-array in each DRAM sub-array group during a refresh cycle and refreshing plural, but not all DRAM sub-arrays in at least one DRAM sub-array group during the refresh cycle.
A method of refreshing a memory device having plural DRAM sub-arrays organized into one or more DRAM sub-array groups, wherein each DRAM sub-array group comprises one or more of the plural DRAM sub-arrays, each DRAM sub-array with plural array rows, the method comprising:
- decoding an address of a memory request;
- indicating which of the plural DRAM sub-arrays are referenced by the memory access request;
- refreshing by use of at least one group refresh technique, in response to the indicating step, at least one array row of at least one of the plural DRAM sub-arrays not referenced by the memory access request, wherein at least one, but not all, of the DRAM sub-arrays in at least one DRAM sub-array group are refreshed during a refresh cycle;
- executing the memory address request, wherein the step of executing is performed contemporaneously with the step of refreshing;
- and
- setting a time period that elapses before refreshing a next at least one array row in the at least one of the plural DRAM sub-arrays.
Dependencies are inferred from the claim text.