Semiconductor memory device with electrically rewritable and non-volatile memory cells arranged therein
AssigneeKabushiki Kaisha Toshiba
InventorsToshihiro Suzuki, Haruki Toda
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes: a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other; a row decoder configured to drive the word lines; and a sense amplifier so coupled to a selected bit line as to compare a cell current with a reference current and sense data of a selected memory cell in the cell array, wherein bit line precharge is performed for a certain time prior to the sense amplifier activation in a data read mode while word line boost is performed in advance of the bit line precharge.
Claims17
A semiconductor memory device comprising:
- a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other;
- a row decoder configured to drive the word lines;
- and
- a sense amplifier so coupled to a selected bit line as to compare a cell current with a reference current and sense data of a selected memory cell in the cell array, wherein
- bit line precharge is performed for a certain time prior to the sense amplifier activation in a data read mode while word line boost is performed in advance of the bit line precharge.
A semiconductor memory device comprising:
- a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other;
- a sense amplifier so coupled to a selected bit line as to sense data of a selected memory cell in the cell array;
- a first bit line precharge circuit so disposed at one end of a bit line near the sense amplifier as to precharge the bit line for a certain time prior to the sense amplifier activation;
- and
- a second bit line precharge circuit so disposed at the other end of the bit line far from the sense amplifier as to precharge the bit line simultaneously with the first bit line precharge circuit.
A semiconductor memory device comprising:
- a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other;
- a sense amplifier so coupled to a selected bit line as to sense data of a selected memory cell in the cell array;
- and
- a bit line precharge circuit attached to the sense amplifier for precharging a bit line for a certain time in advance of the sense amplifier activation, wherein
- the bit line precharge current is supplied in such a manner that it is changed in correspondence with a selected area in the bit line direction in the cell arrays.
A semiconductor memory device comprising:
- a cell array with electrically rewritable and non-volatile memory cells disposed at crossings between bit lines and word lines, which intersect with each other, a plurality of memory cells being connected in series to constitute a NAND string in the cell array;
- and
- a sense amplifier so coupled to a selected bit line as to sense data of a selected memory cell in the cell array, wherein
- data write of the cell array is performed in such a way that memory cells in the NAND string are sequentially selected from the bit line side, so that the word line coupling current input to the sense amplifier at a write-verify time is equalized to that at a normal read time.
Dependencies are inferred from the claim text.