Semiconductor memory device and latency signal generating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsKwang-Il Park, Young-Hyun Jun, Seong-Jin Jang, Ho-Young Song
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Abstract
A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.
Claims18
A semiconductor memory device, comprising:
- a memory cell array storing data during a write operation and outputting data during a read operation;
- mode setting means for setting a CAS latency signal, a burst length signal, and a preamble cycle signal in response to a code signal received during a mode setting operation;
- and
- latency signal generating means for generating a data strobe latency signal which is activated earlier by a cycle corresponding to the preamble cycle signal before data stored in the memory cell array is outputted to an external portion at a cycle corresponding to the CAS latency signal and which is inactivated after maintaining an activation period of the preamble cycle signal by a cycle obtained by adding a cycle corresponding to the burst length signal to a cycle corresponding to the preamble cycle signal.
A semiconductor memory device, comprising:
- a memory cell array storing data during a write operation and outputting data during a read operation;
- mode setting means for setting a CAS latency signal, a burst length signal, and a preamble cycle signal in response to a code signal received during a mode setting operation;
- data strobe latency signal generating means for generating a data strobe latency signal which is activated earlier by a cycle corresponding to the preamble cycle signal before data stored in the memory cell array is outputted to an external portion at a cycle corresponding to the CAS latency signal and which is inactivated after maintaining an activation period of the preamble cycle signal by a cycle obtained by adding a cycle corresponding to the burst length signal to a cycle corresponding to the preamble cycle signal;
- and
- data latency signal generating means for delaying an onset of an activation period of the data strobe latency signal by a cycle corresponding to the preamble cycle signal.
A latency signal generating method of a semiconductor memory device, the method comprising:
- setting a CAS latency signal, a burst length signal, and a preamble cycle signal in response to a code signal during a mode setting operation;
- and
- generating a data strobe latency signal which is activated earlier by a cycle corresponding to the preamble cycle signal before data stored in the memory cell array is outputted to an external portion at a cycle corresponding to the CAS latency signal and which is inactivated after maintaining an activation period of the preamble cycle signal by a cycle obtained by adding a cycle corresponding to the burst length signal to a cycle corresponding to the preamble cycle signal;
- and
- delaying onset of an activation period of the data strobe latency signal by a cycle corresponding to the preamble cycle signal to generate a data latency signal.
Dependencies are inferred from the claim text.