Buffer control circuit, semiconductor memory device for memory module including the buffer control circuit, and control method of the buffer control circuit
AssigneeHynix Semiconductor Inc.
InventorShin Deok Kang
Life of this patent
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Abstract
A buffer control circuit, a semiconductor memory device for a memory module including the buffer control circuit, and a control method of the buffer control circuit, in which power consumption can be reduced. The buffer control circuit includes a first control signal generator that generates an internal buffer control signal in response to write latency signals and internal control signals, and a second control signal generator that generates a buffer control signal in response to the internal buffer control signal and a termination control signal. It is therefore possible to reduce unnecessary power consumption incurred by a data input buffer.
Claims33
A buffer control circuit comprising:
- a first control signal generator that generates an internal buffer control signal in response to write latency signals and internal control signals;
- and
- a second control signal generator that generates a buffer control signal in response to the internal buffer control signal and a termination control signal.
A semiconductor memory device for a memory module, comprising:
- a buffer control circuit that generates a buffer control signal in response to write latency signals, internal control signals, and a termination control signal;
- a plurality of data input buffers connected to a plurality of I/O pads, respectively, through a plurality of data input lines, wherein the data input buffers receive external inputted data, which are respectively inputted to the plurality of I/O pads, respectively, and output internal inputted data to an internal circuit including a core circuit, in response to the buffer control signal during a write operation of the semiconductor memory device;
- and
- a plurality of termination units that are connected to the plurality of data input lines, respectively, and match impedances of the plurality of data input lines to predetermined values, respectively, in response to the termination control signal.
A control method of a buffer control circuit that controls at least one data input buffer in a semiconductor memory device for a memory module, including the at least one data input buffer and at least one termination unit, the method comprising the steps of:
- generating an internal buffer control signal in response to write latency signals and internal control signals;
- and
- generating a buffer control signal in response to the internal buffer control signal and a termination control signal, thereby enabling or disabling the at least one data input buffer.
A semiconductor memory device for a memory module, comprising:
- a plurality of buffer control circuits that generate a plurality of buffer control signals, respectively, in response to write latency signals, internal control signals, and a termination control signal, respectively;
- a plurality of data input buffers connected to a plurality of I/O pads, respectively, through a plurality of data input lines, wherein the data input buffers receive external input data, which are respectively inputted to the plurality of I/O pads, respectively, and output internal input data to an internal circuit including a core circuit, in response to the plurality of buffer control signals, respectively, during a write operation of the semiconductor memory device;
- and
- a plurality of termination units that are connected to the plurality of data input lines, respectively, and match impedances of the plurality of data input lines to predetermined values, respectively, in response to the termination control signal.
Dependencies are inferred from the claim text.