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US 7,453,739 B2Granted
Semiconductor integrated circuit adapted to output pass/fail results of internal operations
AssigneeKabushiki Kaisha Toshiba
InventorsHiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
Life of this patent
Estimating the term…
Abstract
In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
Claims26
A semiconductor memory device comprising:
- a plurality of data cache circuits configured to hold data temporarily;
- a plurality of sense latch circuits connected to the plurality of data cache circuits and configured to sense and latch data read from a plurality of memory cells;
- and
- a control circuit configured to perform a data transfer operation and a first operation,
- wherein the data transfer operation is an operation to transfer data from the plurality of sense latch circuits to the plurality of data cache circuits, and the first operation is an operation to latch data of a selected memory cell into a corresponding one of the plurality of sense latch circuits, the data transfer operation being performed by inputting a first command or a first command sequence, the first operation being performed automatically after the data transfer operation terminates, and a first ready/busy signal goes to a busy status during the data transfer operation.
2 more elements
A semiconductor memory device comprising:
- a plurality of data cache circuits configured to hold data temporarily;
- a plurality of sense latch circuits connected to the plurality of data cache circuits and configured to latch data to be programmed into a plurality of memory cells;
- and
- a control circuit configured to perform a data transfer operation and a first operation,
- wherein the data transfer operation is an operation to transfer data from the plurality of data cache circuits to the plurality of sense latch circuits, and the first operation is an operation to write data which is latched into a corresponding one of the plurality of sense latch circuits to a selected memory cell, the data transfer operation being performed by inputting a first command or a first command sequence, the first operation being performed automatically after the data transfer operation terminates, and a first ready/busy signal goes to a busy status during the data transfer operation.
2 more elements
A semiconductor memory device comprising:
- a plurality of data cache circuits configured to hold data temporarily;
- a plurality of sense latch circuits connected to the plurality of data cache circuits and configured to sense and latch data read from a plurality of memory cells;
- and
- a control circuit configured to perform a first operation and a data transfer operation,
- wherein the first operation is an operation to latch data of a selected memory cell into a corresponding one of the plurality of sense latch circuits, and the data transfer operation is an operation to transfer data from the plurality of sense latch circuits to the plurality of data cache circuits, the first operation being performed by inputting a first command or a first command sequence, the data transfer operation being performed automatically after the first operation terminates, and a first ready/busy signal goes to a busy status during the data transfer operation.
2 more elements
A semiconductor memory device comprising:
- a plurality of data cache circuits configured to hold data temporarily;
- a plurality of sense latch circuits connected to the plurality of data cache circuits and configured to sense and latch data read from a plurality of memory cells;
- and
- a control circuit configured to perform a first operation and a data transfer operation,
- wherein the first operation is an operation to latch data of a selected memory cell into a corresponding one of the plurality of sense latch circuits, and the data transfer operation is an operation to transfer data from the plurality of sense latch circuits to the plurality of data cache circuits, one of the first operation and the data transfer operation being performed by inputting a first command or a first command sequence, the other being performed automatically after the one of the first operation or the data transfer operation terminates, and a first ready/busy signal goes to a busy status during the data transfer operation.
2 more elements
A semiconductor memory device comprising:
- a plurality of data cache circuits configured to hold data temporarily;
- a plurality of sense latch circuits connected to the plurality of data cache circuits and configured to sense and latch data read from a plurality of memory cells in a program verify operation;
- and
- a control circuit configured to perform a data transfer operation and a first operation;
- wherein the data transfer operation is an operation to transfer data from a corresponding one of the plurality of data cache circuits and the plurality of sense latch circuits to the other, and the first operation is an operation to latch data of a selected memory cell into a corresponding one of the plurality of sense latch circuits or a corresponding one of the plurality of data cache circuits, the data transfer operation being performed by inputting a first command or a first command sequence, the first operation being performed automatically after the data transfer operation terminates, and a first ready/busy signal goes to a busy status during the data transfer operation.
2 more elements
A semiconductor memory device comprising:
- a plurality of data cache circuits configured to hold data temporarily;
- a plurality of sense latch circuits connected to the plurality of data cache circuits and configured to sense and latch data read from a plurality of memory cells and latch data to be programmed into the plurality of memory cells in a program verify operation;
- and
- a control circuit configured to perform a first operation and a data transfer operation,
- wherein the first operation is an operation to transfer data which is held in one of a selected memory cell and a corresponding one of the plurality of sense latch circuits to the other and holding, and the data transfer operation is an operation to transfer data from one of the plurality of data cache circuits and the plurality of sense latch circuits to the other, one of the first operation and the data transfer operation being performed by inputting a first command or a first command sequence, the other being performed automatically after one of the first operation and the data transfer operation terminates, and a first ready/busy signal goes to a busy status during the data transfer operation.
2 more elements
Dependencies are inferred from the claim text.