Semiconductor device

A semiconductor device which is activated in accordance with a command, comprising:

• clock terminals which receive clock signals to which the command is synchronized;
• a plurality of first terminals which receive input signals different from the clock signals;
• a plurality of first input buffers which are coupled to the plurality of first terminals;
• and
• a plurality of memory banks which store data,
• wherein the semiconductor device is capable of a burst write operation which inputs a predetermined number of data to be stored in the plurality of memory banks in response to the command,
• wherein a respective differential amplifier of at least one of the plurality of first input buffers has an active state and an inactive state, and
• wherein the differential amplifier of the at least one first input buffer is changed from the active state to the inactive state in response to an end of the burst write operation.

A semiconductor device which is activated in accordance with a command, comprising:

• a first clock terminal which receives a clock signal to which the command is synchronized;
• a second clock terminal which receives an inverse clock signal to which the command is synchronized;
• a plurality of first terminals which receive respective input signals different from the clock signal and the inverse clock signal;
• and
• a plurality of first input buffers each of which has a differential amplifier coupled to a respective one of the plurality of first terminals,
• wherein the semiconductor device is capable of a burst write operation which inputs a predetermined number of data in response to the command,
• wherein the differential amplifier of each of the plurality off first input buffers has an active state and an inactive state, and
• wherein the differential amplifier of each of the plurality of first input buffers is changed from the active state to the inactive state in response to an end of the burst write operation.

A double data rate synchronous dynamic random access memory, comprising:

• a plurality of first terminals which receive commands;
• a second terminal which receives an input signal which is different from the commands;
• and
• an first input buffer which is coupled to the second terminal;
• wherein the double data rate synchronous dynamic random access memory is capable of a burst write operation which inputs a predetermined number of data in response to one of the commands,
• wherein the first input buffer has an active state and an inactive state, and
• wherein the first input buffer is changed from the active state to the inactive state in response to an end of the burst write operation.

A double data rate synchronous dynamic random access memory, comprising:

• a first external terminal which receives data;
• and
• a first input buffer connected to said first external terminal,
• wherein a signal interface of said first input buffer is an SSTL interface,
• wherein the double data rate synchronous dynamic random access memory is capable of a burst write operation which inputs a predetermined number of data in response to a write command,
• wherein said first input buffer has an active state and an inactive state, and
• wherein said first input buffer is changed from the active state to the inactive state in response to an end of the burst write operation.