Methods of erasing and designing electrically erasable charge trap nonvolatile memory cells having erase threshold voltage that is higher than an initial threshold voltage

A method of erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the erasing method comprising:

• applying an erase voltage to the gate for a time interval that is sufficient to lower a threshold voltage of the transistor from the program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage;
• wherein the time interval is determined by performing the following:
• setting an endurance specification for a memory cell;
• performing an endurance test of a memory cell using an initial time interval;
• and
• repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval to obtain the time interval that meets the endurance specification.

A method of determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the time interval determining method comprising:

• setting an endurance specification for a memory cell that includes a critical erase voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage;
• performing an endurance test of a memory cell using an initial time interval;
• and
• repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval to obtain the time interval that meets the endurance specification including the critical erase voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage.

A method of determining a time interval for erasing a programmed electrically erasable charge trap nonvolatile memory cell that includes a transistor in an integrated circuit substrate, the transistor including a gate having a charge trapping region therein, the transistor having an initial threshold voltage and a program threshold voltage that is higher than the initial threshold voltage, the time interval determining method comprising:

• performing an endurance test of a memory cell using an initial time interval;
• attempting to successfully read the memory cell;
• and
• repeatedly performing the endurance test of a memory cell using a time interval that is increased or decreased from the initial time interval, based upon whether the attempting was able to successfully read the memory cell.