US 7,453,735 B2Granted

Non-volatile memory and control with improved partial page program capability

AssigneeSanDisk Corporation

InventorsYan Li, Yupin Kawing Fong, Toru Miwa

Life of this patent

Estimating the term…

Loading patent…

Abstract

In a non-volatile memory programming scheme where the memory cells are programmed in two or more sequential programming passes, when there is insufficient host data to program at least some of the memory cells during the second pass, some of the memory cells may be programmed to the wrong threshold voltage. This can be prevented by modifying the programming scheme so that this does not occur. In one implementation, this is accomplished by choosing a code scheme, which does not cause the memory cells to be programmed to the wrong threshold voltage during the second programming pass, or by programming the memory cells in accordance with substitute data that would not cause the cells to be programmed to an erroneous state.

Claims36

Dependent claims

A storage device comprising:

programmable non-volatile memory cells of a type that store data as corresponding different levels of charge in charge storage elements, the charge storage levels of said elements being in a reset charge storage level distribution prior to the programming;
and
means for programming the charge storage elements in at least two passes, wherein during a first pass, selected ones of the elements are programmed into a first storage level distribution, and during a subsequent second pass, selected ones of the elements in the reset charge storage level distribution are programmed into a second storage level distribution and selected ones of the elements in the first storage level distribution are programmed into a third storage level distribution, the second storage level distribution being between the reset and the first storage level distributions, the first storage level distribution being between the second and third storage level distributions;
wherein when there is insufficient host data to program at least one of the elements during the second pass, said at least one element having been programmed into the first storage level during the first pass, the programming means causes the charge storage level of said at least one element to be below the charge storage levels of the third storage level distribution after the second pass.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 11/867,598Filed 4 Oct 2007 · continuation
Priority: 23 Apr 2004
Published: US 2008/0025099 A131 Jan 2008
Granted: 18 Nov 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Family

Application10/830,824Parent of this continuation · filed 23 Apr 2004
Application11/381,972Parent of this continuation · filed 5 May 2006
US 2008/0025099 A1Pre-grant publication · published 31 Jan 2008
US 7,280,396 B2Parent of this continuation
US 7,057,939 B2Parent of this continuation
US 2005/0237814 A1Published application
US 2006/0203561 A1Published application
US 7,453,735 B2This patent

From the US filing history. Foreign family members aren’t listed.