Method for programming memory cells including transconductance degradation detection

A method for identifying a degraded memory cell comprising:

• applying a first read voltage to a control gate of the memory cell;
• comparing a first read current through the memory cell resulting from the first read voltage with a first threshold;
• applying a second read voltage to the control gate of the memory cell if the first read current is less than the first threshold;
• comparing a second read current through the memory cell resulting from the second read voltage with a second threshold;
• and
• identifying the memory cell as being degraded if the second read current is greater than the second threshold.

A memory comprising:

• a memory cell;
• a first read circuit configured to apply a first read voltage to the memory cell and compare a first read current through the memory cell resulting from the first read voltage with a first threshold;
• a second read circuit configured to apply a second read voltage to the memory cell if the first read current is less than the first threshold and configured to compare a second read current through the memory cell resulting from the second read voltage with a second threshold;
• and
• a programming circuit configured to apply a programming voltage signal to the memory cell if the second read current is greater than the second threshold, wherein the programming voltage signal at least partially programs the memory cell.

A method of programming a memory cell comprising:

• applying a first read voltage greater than a reference voltage to a control gate of the memory cell;
• applying a second read voltage less than first reference to the control gate of the memory cell;
• comparing a first read current through the memory cell resulting from the first read voltage with a first current threshold;
• comparing a second read current through the memory cell resulting from the second read voltage with a second current threshold;
• and
• applying a programming voltage signal to the control gate of the memory cell in response to the memory cell not being in a target program state.