Apparatus for eliminating leakage current of a low Vt device in a column latch

A high-voltage latch system for a non-volatile memory, comprising:

• a HV terminal that is coupled to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation and that is coupled to a HIGH-VOLTAGE supply voltage during a high-voltage write mode of operation;
• a cross-coupled high-voltage CMOS latch having a latch input node B and a latch output node A;
• an input buffer, including:
• a first PMOS pull-up transistor and a second PMOS pull-up transistor coupled in series between the HV terminal and the latch input node B of the cross-coupled high-voltage CMOS latch;
• a first NMOS pull-down transistor and a second NMOS pull-down transistor coupled in series between the latch input node B of the cross-coupled high-voltage CMOS latch and the ground terminal;
• a DATA INPUT terminal coupled to a gate of the first PMOS pull-up transistor and a gate of the second NMOS pull-down transistor;
• a HV LOAD terminal which is coupled to a gate terminal of the second PMOS pull-up transistor and at which is provided a LOW LOADHVB signal to turn on the second PMOS pull-up transistor;
• a LOAD terminal which is coupled to a gate of the second NMOS pull-down transistor and at which is provided a HIGH LOAD signal to turn on the second NMOS pull-down transistor;
• and
• wherein the LOW LOADHVB signal and the HIGH LOAD signal are provided during a load-data mode of operation;
• wherein the input buffer isolates the DATA INPUT terminal from the high-voltage CMOS latch.

A high-voltage column latch system for a non-volatile memory, comprising:

• a HV terminal that is coupled to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation and that is coupled to a HIGH-VOLTAGE supply voltage during a high-voltage write mode of operation;
• an input inverter, including:
• a first PMOS pull-up transistor and a second PMOS pull-up transistor coupled in series between the HV terminal and the latch input node B of the cross-coupled high-voltage CMOS latch;
• a first NMOS pull-down transistor and a second NMOS pull-down transistor coupled in series between the latch input node B of the cross-coupled high-voltage CMOS latch and the ground terminal;
• a DATA INPUT terminal coupled to a gate of the first PMOS pull-up transistor and a gate of the second NMOS pull-down transistor;
• an HV LOAD terminal which is coupled to a gate terminal of the second PMOS pull-up transistor and at which is provided a LOADHVB signal;
• and
• a LOAD terminal which is coupled to a gate of the first NMOS pull-down transistor and at which is provided a LOAD signal;
• wherein a LOW LOADHVB signal and a HIGH LOAD signal are provided during a load-data mode of operation;
• a cross-coupled high-voltage CMOS latch, including:
• a first CMOS inverter and a second CMOS inverter, each having respective input and output terminals, and each being coupled between the HV terminal and a ground terminal;
• the input terminal of the second CMOS inverter and the output terminal of the first CMOS inverter are coupled to a latch input node B;
• the input terminal of the first CMOS inverter and the output terminal of the second CMOS output terminal are coupled to a latch output node A;
• said first CMOS inverter having a first PMOS pull-up transistor coupled between the HV terminal and the latch input node B, said first CMOS inverter having a first NMOS pull-down transistor coupled between the latch input node A and the ground terminal;
• said second CMOS inverter having a second PMOS pull-up transistor coupled between the HV terminal and the latch output node A;
• said second CMOS inverter having a second high-voltage, low-threshold NMOS pull-down transistor that is coupled to the ground terminal;
• wherein the input buffer isolates the DATA INPUT terminal from the high-voltage CMOS latch.

A high-voltage latch system for a non-volatile memory, comprising:

• a high-voltage terminal that is coupled to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation and that is coupled to a high supply voltage during a high-voltage write mode of operation;
• a cross-coupled high-voltage CMOS latch that is coupled between the high-voltage terminal and a ground terminal and that has a latch input node and a latch output node;
• an input buffer that is coupled between the high-voltage terminal and the ground terminal, the input buffer being coupled to an input terminal that is adapted to be coupled to a bit line of the non-volatile memory, the input buffer including an output terminal coupled to the latch input node and a first transistor coupled to load data from the input terminal to the latch input node of the cross-coupled high-voltage CMOS latch during the load-data mode of operation;
• and
• wherein the input buffer includes a second transistor that is coupled to substantially isolate the input terminal from the cross-coupled high-voltage CMOS latch during the high-voltage write mode of operation.

A high-voltage latch system for a non-volatile memory, comprising:

• a high-voltage terminal that is coupled to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation and that is coupled to a high supply voltage during a high-voltage write mode of operation;
• a cross-coupled high-voltage CMOS latch having a latch input node and a latch output node;
• an input buffer, including:
• a first PMOS pull-up transistor and a second PMOS pull-up transistor coupled in series between the high-voltage terminal and the latch input node of the cross-coupled high-voltage CMOS latch;
• a first NMOS pull-down transistor and a second NMOS pull-down transistor coupled in series between the latch input node of the cross-coupled high-voltage CMOS latch and a ground terminal;
• an input terminal coupled to a gate of the first PMOS pull-up transistor and a gate of the first NMOS pull-down transistor;
• a first load terminal that is coupled to a gate terminal of the second PMOS pull-up transistor and is coupled to receive a first load signal to control the second PMOS pull-up transistor;
• a second load terminal that is coupled to a gate of the second NMOS pull-down transistor and is coupled to receive a second load signal to control the second NMOS pull-down transistor;
• and
• wherein the first load signal is low and the second load signal is high during the load-data mode of operation;
• and
• wherein the input buffer is coupled to substantially isolate the input terminal from the cross-coupled high-voltage CMOS latch during the high-voltage write mode of operation.

A high-voltage column latch system for a non-volatile memory, comprising:

• a high-voltage terminal that is coupled to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation and that is coupled to a high supply voltage during a high-voltage write mode of operation;
• an input inverter, including:
• a first PMOS pull-up transistor and a second PMOS pull-up transistor coupled in series between the high-voltage terminal and a latch input node of a cross-coupled high-voltage CMOS latch;
• a first NMOS pull-down transistor and a second NMOS pull-down transistor coupled in series between the latch input node of the cross-coupled high-voltage CMOS latch and a ground terminal;
• an input terminal that is coupled to a gate of the first PMOS pull-up transistor and a gate of the first NMOS pull-down transistor;
• a first load terminal that is coupled to a gate terminal of the second PMOS pull-up transistor and is coupled to receive a first load signal;
• and
• a second load terminal that is coupled to a gate of the second NMOS pull-down transistor and is coupled to receive a second load signal;
• wherein the first load signal is low and the second load signal is high during the load-data mode of operation;
• and
• the cross-coupled high-voltage CMOS latch includes:
• a first CMOS inverter and a second CMOS inverter, each having respective input and output terminals, and each being coupled between the high-voltage terminal and the ground terminal;
• the input terminal of the second CMOS inverter and the output terminal of the first CMOS inverter are coupled to the latch input node;
• the input terminal of the first CMOS inverter and the output terminal of the second CMOS output terminal are coupled to a latch output node;
• said first CMOS inverter includes a first latch PMOS pull-up transistor coupled between the high-voltage terminal and the latch input node, said first CMOS inverter having a first latch NMOS pull-down transistor coupled between the latch input node and the ground terminal;
• said second CMOS inverter includes a second latch PMOS pull-up transistor coupled between the high-voltage terminal and the latch output node;
• said second CMOS inverter includes a second latch NMOS pull-down transistor that is coupled to the ground terminal;
• wherein the input buffer substantially isolates the input terminal from the cross-coupled high-voltage CMOS latch.

An apparatus comprising:

• a first terminal that is coupled to a supply voltage during a standby mode of operation and during a load-data mode of operation and that is coupled to a high supply voltage during a high-voltage write mode of operation;
• a latch circuit coupled between the first terminal and a reference potential and having a latch input node and a latch output node;
• an input buffer circuit coupled between an input terminal and the latch input node, the input buffer including:
• a first transistor coupled between the input terminal and the latch input node to load data from the input terminal to the latch input node during the load-data mode of operation;
• and
• a second transistor to enable the input buffer circuit to load data from the input terminal to the latch input node during the load-data mode of operation, wherein the second transistor substantially isolates the input terminal from the latch input node during the high-voltage write mode of operation.

A method comprising:

• coupling a supply voltage to a first terminal during a first mode of operation and during a load-data mode of operation of a latch circuit;
• switching on an enable transistor in an input buffer circuit coupled to an input terminal to enable the input buffer circuit during the load-data mode of operation;
• loading data from the input terminal to a latch input node of the latch circuit through a second transistor in the input buffer circuit during the load-data mode of operation;
• coupling a high supply voltage to the first terminal during a high-voltage write mode of operation of the latch circuit;
• and
• switching off the enable transistor in the input buffer circuit to substantially isolate the input terminal from the latch circuit during the high-voltage write mode of operation.