Phase change memory device and memory cell array thereof
AssigneeSamsung Electronics Co., Ltd.
InventorsByung-Gil Choi, Jong-Soo Seo, Young-Kug Moon, Bo-Tak Lim, Su-Yeon Kim
Life of this patent
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Abstract
A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.
Claims20
A memory cell array of a phase change memory device, comprising:
- first and second cell regions;
- a first local bitline connected to the first cell region;
- a second local bitline connected to the second cell region;
- and
- a select region located between the first and second cell regions, separating the first cell region from the second cell region, and connecting the first and second local bitlines with a global bitline in response to a local select signal,
- wherein the select region comprises a transistor having a gate for receiving the local select signal, a first terminal connected to the global bitline and a second terminal connected to both the first local bitline and the second local bitline.
A phase change memory device, comprising:
- a memory cell array comprising a plurality of memory cells;
- and
- a write driver for supplying a program current to the memory cell array through a global bitline,
- wherein the memory cell array comprises first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region located between the first and second cell regions, separating the first cell region from the second cell region and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal, and
- wherein the select region comprises a transistor having a gate for receiving the local select signal, a first terminal connected to the global bitline and a second terminal connected to both the first local bitline and the second local bitline.
A memory cell array of a phase change memory device, comprising:
- a first cell region and a second cell region;
- a first local bitline connected to the first cell region;
- a second local bitline connected to the second cell region;
- and
- a select region located between the first cell region and the second cell region, the select region connecting the first local bitline and the second local bitline to a global bitline in response to a local select signal during a write operation,
- wherein the first and second cell regions comprise a plurality of memory cells respectively connected to the first and second local bitlines.
A resistance variable memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a write driver for supplying a program current to the memory cell array through a global bitline,
- wherein the memory cell array comprises first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region located between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal for a program operation.
Dependencies are inferred from the claim text.