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US 7,453,717 B2Granted
Three-state memory cell
AssigneeSTMicroelectronics S.r.l.
InventorsSylvie Wuidart, Luc Wuidart
Life of this patent
Estimating the term…
Abstract
A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.
Claims33
A method for reading a memory cell with first and second memory states, the memory cell including a first programmable resistance element having a programmable resistance, the method comprising:
- driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the detecting step includes:
- detecting the first memory state by detecting that the first electrical quantity logically equals the second electrical quantity;
- and
- detecting the second memory state by detecting that the first electrical quantity does not logically equal the second electrical quantity.
4 more elements
A method for reading a memory cell with first and second memory states, the memory cell including a first programmable resistance element having a programmable resistance, the method comprising:
- driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the detecting step includes:
- detecting the first memory state by detecting that the first electrical quantity is greater than the second electrical quantity;
- and
- detecting the second memory state by detecting that the first electrical quantity is less than the second electrical quantity.
4 more elements
A method for reading a memory cell with first and second memory states, the memory cell including a first programmable resistance element having a programmable resistance, the method comprising:
- driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein driving the first programmable resistance element with the first current includes switching a first switchable resistor into connection between the first programmable resistance element and a first source terminal and driving the first programmable resistance element with the second current includes switching a second switchable resistor into connection between the first programmable resistance element and the first source terminal.
1 more element
A memory device, comprising:
- a memory cell that includes a first programmable resistance element having a programmable resistance;
- means for driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- means for driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- means for detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the detecting means includes:
- means for detecting the first memory state by detecting that the first electrical quantity logically equals the second electrical quantity;
- and
- means for detecting the second memory state by detecting that the first electrical quantity does not logically equal the second electrical quantity.
5 more elements
A memory device, comprising:
- a memory cell that includes a first programmable resistance element having a programmable resistance;
- means for driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- means for driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- means for detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the detecting means includes:
- means for detecting the first memory state by detecting that the first electrical quantity is greater than the second electrical quantity;
- and
- means for detecting the second memory state by detecting that the first electrical quantity is less than the second electrical quantity.
5 more elements
A memory device, comprising:
- a memory cell that includes a first programmable resistance element having a programmable resistance;
- means for driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- means for driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- means for detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the means for driving the first programmable resistance element with the first current include a first resistor and a first switch coupled together between a first source terminal and the first programmable resistance element and the means for driving the first programmable resistance element with the second current include a second resistor and a second switch coupled together between the first source terminal and the first programmable resistance element.
2 more elements
A memory device, comprising:
- a memory cell that includes a first programmable resistance element having a programmable resistance;
- means for driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- means for driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- means for detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the means for measuring the first electrical quantity includes a sense amplifier having a first input terminal coupled to the first programmable resistance element, a second input terminal coupled to a reference voltage, and an output terminal that provides a logical output indicating whether the first electrical quantity exceeds the reference voltage.
2 more elements
A memory device, comprising:
- a memory cell that includes a first programmable resistance element having a programmable resistance;
- means for driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- means for driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- means for detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the first programmable resistance element is a polysilicon resistor.
2 more elements
A memory device, comprising:
- a memory cell that includes a first programmable resistance element having a programmable resistance;
- means for driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- means for driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- means for detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the first programmable resistance element is one-time programmable.
2 more elements
A memory device, comprising:
- a memory cell that includes a first programmable resistance element having a programmable resistance;
- means for driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- means for driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- means for detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the means for detecting include:
- a first flip-flop connected to the first programmable resistance element and structured to store the first electrical quantity;
- a second flip-flop connected to the first programmable resistance element and structured to store the second electrical quantity;
- and
- a comparator coupled to outputs of the flip-flops and structured to compare the first electrical quantity to the second electrical quantity.
6 more elements
A memory device, comprising:
- a memory cell including a first programmable resistance element having a programmable resistance;
- a first switchable resistor coupled between a first source terminal and the first programmable resistance element;
- a second switchable resistor coupled between the first source terminal and the first programmable resistance element;
- a read circuit coupled to the first programmable resistance element and structured to detect a first memory state of the memory cell by comparing a first electrical quantity, at the first programmable resistance element when a first current is driven through the first switchable resistor to the first programmable resistance element, with a second electrical quantity at the first programmable resistance element when a second current is driven through the second switchable resistor to the first programmable resistance element.
1 more element
A method for reading a memory cell with first and second memory states, the memory cell including a first programmable resistance element having a programmable resistance, the method comprising:
- driving the first programmable resistance element with a first current and measuring a first electrical quantity at the first programmable resistance element;
- driving the first programmable resistance element with a second current and measuring a second electrical quantity at the first programmable resistance element;
- and
- detecting the first and second memory states by comparing the first electrical quantity with the second electrical quantity, wherein the first programmable resistance element is a polysilicon resistor, wherein driving the first programmable resistance element with the first current includes switching a first switchable resistor into connection between the first programmable resistance element and a first source terminal and driving the first programmable resistance element with the second current includes switching a second switchable resistor into connection between the first programmable resistance element and the first source terminal.
1 more element
Dependencies are inferred from the claim text.