Power-saving multibit delta-sigma converter

A power-saving multibit delta-sigma converter comprising:

• (a) an input for an analog input signal and an output for a digital output signal;
• (b) a digital-to-analog converter having a bit width N and serving to convert the digital output signal to an analog feedback signal;
• (c) a summing device for forming the difference between the input signal and the feedback signal;
• (d) a filter for filtering the difference signal;
• and
• (e) a clocked quantizing device for quantizing the filtered difference signal to form the digital output signal with the bit width N;
• wherein the quantizing device applying a potential offset to the filtered signal and having fewer than 2N−1 comparators which compare the filtered signal to which said potential offset has been applied with a respective reference potential associated with the respective comparator and which each output a comparison result to a decoder, which generates the digital output signal from the comparison results, and the potential offset being tracked in a manner dependent on a previous comparison result;
• and
• wherein the quantizing device has at least one first, second and third comparator each having a first and a second input and an output, the filtered signal being applied to the first inputs, the outputs each supplying a comparison result and a first, second and third reference potential being switched to the second inputs, the second reference potential lying between the first and third reference potentials and being closest to the potential of the filtered signal.