Circuit, control system, IC, transmitting and receiving apparatus, control method and program

A control system comprising:

• a first PLL unit which is a high-frequency jitter suppression unit providing a first signal output;
• a second PLL unit receiving said first signal output and which is a low-frequency wander suppression unit providing a second signal output;
• and
• a third PLL unit receiving said second signal output and which is a reproduction clock unit providing a third signal output, the third signal output being fed back to the first PLL unit so that the first to third PLL units are connected to form a multiloop synthesizer configuration.

A control method under a multiloop synthesizer configuration that is formed by a first PLL unit which is a high-frequency jitter suppression unit, a second PLL unit which is a low-frequency wander suppression unit and a third PLL unit which is a reproduction clock unit,

• the method in the first PLL unit comprising the steps of:
• dividing a reference clock into a phase comparison frequency with a first 1/N unit;
• dividing a multiloop clock from the third PLL unit into the phase comparison frequency with a first 1/M unit;
• performing a phase comparison process with a first phase detector unit;
• amplifying a direct-current component with a first amplifier unit;
• and
• controlling an output frequency by a direct-current signal with a first VCO unit,
• the method in the second PLL unit comprising the steps of:
• dividing a signal from the first PLL unit into the phase comparison frequency with a second 1/N unit;
• dividing a generation clock of the second PLL unit into the phase comparison frequency with a second 1/M unit;
• performing the phase comparison process with a second phase detector unit;
• amplifying the direct-current component with a second amplifier unit;
• and
• controlling the output frequency by the direct-current signal with a second VCO unit, and
• the method in the third PLL unit comprising the steps of:
• dividing a signal from the second PLL unit into the phase comparison frequency with a third 1/N unit;
• dividing a generation clock of the third PLL unit into the phase comparison frequency with a third 1/M unit;
• performing the phase comparison process with a third phase detector unit;
• amplifying the direct-current component with a third amplifier unit;
• and
• controlling the output frequency by the direct-current signal with a third VCO unit.

A program implemented on a computer-readable recording medium for a first PLL unit, a second PLL unit and a third PLL unit, the first PLL unit being a high-frequency jitter suppression unit, the second PLL unit being a low-frequency wander suppression unit, the third PLL unit being a reproduction clock unit, the first to third PLL units being connected to form a multiloop synthesizer configuration,

• the program causes the first PLL unit to execute the following:
• dividing a reference clock into a phase comparison frequency with a first 1/N unit;
• dividing a multiloop clock from the third PLL unit into the phase comparison frequency with a first 1/M unit;
• performing a phase comparison process with a first phase detector unit;
• amplifying a direct-current component with a first amplifier unit;
• and
• controlling an output frequency by a direct-current signal with a first VCO unit,
• the program causes the second PLL unit to execute the following:
• dividing a signal from the first PLL unit into the phase comparison frequency with a second 1/N unit;
• dividing a generation clock of the second PLL unit into the phase comparison frequency with a second 1/M unit;
• performing the phase comparison process With a second phase detector unit;
• amplifying the direct-current component with a second amplifier unit;
• and
• controlling the output frequency by the direct-current signal with a second VCO unit, and
• the program causes the third PLL unit to execute the following:
• dividing a signal from the second PLL unit into the phase comparison frequency with a third 1/N unit;
• dividing a generation clock of the third PLL unit into the phase comparison frequency with a third 1/M unit;
• performing the phase comparison process with a third phase detector unit;
• amplifying the direct-current component with a third amplifier unit;
• and
• controlling the output frequency by the direct-current signal with a third VCO unit.