MTCMOS flip-flop, circuit including the MTCMOS flip-flop, and method of forming the MTCMOS flip-flop

A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop comprising:

• a first stage charging or discharging an internal node in response to an input data signal, a clock signal, and a sleep signal activated in a sleep mode;
• a second stage charging or discharging an output node in response to a signal apparent at the internal node, the clock signal, and a combination of the clock signal and the sleep signal, and storing an output data signal generated by charging or discharging the output node;
• a clock delay unit delaying the clock signal in an active mode;
• wherein the first stage or the second stage comprises a first leakage break transistor gated by an output signal of the crock delay unit in sleep mode and turned off in response to an activated sleep signal, thereby breaking a leakage current path during sleep mode;
• wherein the clock delay unit is responsive to the clock signal and the sleep signal and comprises:
• a first inverter inverting the clock signal;
• a second inverter inverting an output signal of the first inverter;
• and,
• a NOR gate performing a NOR operation on an output signal of the second inverter and the sleep signal;
• and,
• wherein the first and second inverters comprise transistors having a low threshold voltage, and the NOR gate comprises a transistor having a high threshold voltage.

A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop comprising:

• a first stage charging or discharging an internal node in response to an input data signal, a clock signal, and a sleep signal activated in a sleep mode;
• and,
• a second stage comprising:
• a first transistor arranged in a first charge path allowing an output node to be charged in response to a signal apparent at the internal node,
• a plurality of second transistors arranged in a first discharge path allowing the output node to be discharged in response to the signal apparent at the internal node, the clock signal, and a combination of the clock signal and the sleep signal,
• wherein the second stage stores an output data signal generated by charging or discharging the output node, and
• wherein one of the second transistors is a leakage break transistor having a threshold voltage relatively higher than a threshold voltage for other transistors in the plurality of second transistors and being turned off in response to an activated sleep signal to thereby break a leakage current path associated with the output node.

A multi-threshold voltage complementary metal oxide semiconductor (MTCMOS) flip-flop comprising:

• a clock delay unit delaying a clock signal in an active mode in which a sleep signal is inactivated and being inactivated in a sleep mode in which the sleep signal is activated;
• a first stage charging or discharging an internal node in response to an input data signal, the clock signal, and an output signal of the clock delay unit;
• and,
• a second stage charging or discharging an output node in response to a signal apparent at the internal node, the clock signal, and the output signal of the clock delay unit, and storing an output data signal generated by charging or discharging the output node,
• the second stage comprising:
• a first transistor arranged in a first charge path allowing an output node to be charged in response to a signal apparent at the internal node,
• a plurality of second transistors arranged in a first discharge path allowing the output node to be discharged in response to the signal apparent at the internal node, the clock signal, and a combination of the clock signal and the sleep signal, and
• wherein one of the second transistors is a first leakage break transistor having a threshold voltage relatively higher than a threshold voltage for other transistors in the plurality of second transistors and being turned off in response to an activated sleep signal to thereby break a leakage current path associated with the output node.