Dynamic frequency divider with improved leakage tolerance
AssigneeAltera Corporation
InventorsShoujun Wang, Haitao Mei, Bill Bereza
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Abstract
A dynamic frequency divider circuit with improved leakage tolerance supports a wide frequency range. During the evaluation phase, (1) the input signals can be prevented from changing states, (2) the leakage can be reduced, or (3) both can be implemented to generate the correct output signals. In a architecture-level approach, two dynamic flip-flops can be coupled together. In a circuit-level approach, the dynamic flip-flop can include (1) two additional clocked PMOS transistor added to the inputs of the dynamic flip-flop, or (2) two additional pull-up PMOS transistors to counteract the subthreshold leakage in the NMOS transistors.
Claims10
A dynamic frequency divider circuit comprising:
- a first positive-channel metal-oxide semiconductor (PMOS) transistor having a first source, a first gate, and a first drain;
- a second PMOS transistor having a second source, a second gate, and a second drain, wherein the first gate and the second gate are coupled to receive a first signal having a first frequency;
- and
- a sense amplifier based flip-flop comprising a first input coupled to the first drain, a second input coupled to the second drain, a third input coupled to receive the first signal, a first output coupled to the second source, and a second output coupled to the first source, wherein the first output generates a second signal having a second frequency that is a multiple of the first frequency.
A dynamic frequency divider circuit comprising:
- a sense amplifier based flip-flop comprising (1) a sense amplifier having a cross-coupled inverter and (2) a set-reset latch coupled to the sense amplifier, the sense amplifier based flip-flop having a first input, a second input, a third input coupled to receive a first signal having a first frequency, a first output coupled to the second input, and a second output coupled to the first input, wherein the first output generates a second signal having a second frequency that is a multiple of the first frequency;
- a first positive-channel metal-oxide semiconductor (PMOS) transistor coupled across a first half of the cross-coupled inverter, and operative to pull-up the voltage at a first output of the sense amplifier when the first output is binary “1;” and
- a second PMOS transistor coupled across a second half of the cross-coupled inverter, and operative to pull-up the voltage at the second output of the sense amplifier when the second output is binary “1.”
Dependencies are inferred from the claim text.