High frequency divider state correction circuit

A self-correcting state circuit, comprising:

• a first flip flop configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input;
• a second flip flop coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the second data input;
• a first correction circuit coupled to the second flip flop and configured to generate a corrected output;
• and
• a third flip flop coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input wherein the first correction circuit is further configured to generate the corrected output based on the inverse of the first output, the inverse of the second output, and the inverse of the third output.