Clock translator and parallel to serial converter
AssigneeSigmatel, Inc.
InventorDarrell Eugene Tinker
Life of this patent
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Abstract
A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
Claims25
A clock translator, comprising:
- a first input to receive a first reference clock signal;
- a second input to receive a second reference clock signal;
- an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to a frequency of the first reference clock signal but having a resolution based on at least a portion of the second reference clock signal;
- wherein the bit rate clock signal is provided to a parallel to serial converter.
A clock translator, comprising:
- a first input to receive a first reference clock signal;
- a second input to receive a second reference clock signal;
- an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to a frequency of the first reference clock signal but having a resolution based on at least a portion of the second reference clock signal;
- and
- a third input to receive a sample rate control input, wherein the first ratio is controlled by the sample rate control input.
Dependencies are inferred from the claim text.