Comparator and method of implementing a comparator in a device having programmable logic
AssigneeXilinx, Inc.
InventorsJorge Ernesto Carrillo, Raj Kumar Nagarajan, James M. Pangburn, Navaneethan Sundaramoorthy
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Abstract
A method of implementing a comparator in a device having programmable logic is described. The method comprises implementing a first comparison function in a first lookup table; implementing a second comparison function in a second lookup table; and using an output associated with the first comparison function to select an output of the comparator. A device having programmable logic comprising a comparator is also described.
Claims20
A method of implementing a comparator in a device having programmable logic, the method comprising:
- implementing a first comparison function in a first lookup table;
- implementing a second comparison function in a second lookup table, the second comparison function different than the first comparison function;
- and
- using an output associated with the first comparison function to select an output of the comparator.
A method of implementing a comparator in a device having programmable logic, the method comprising:
- providing a multistage comparator having a stage receiving most significant bits of a compared value and one or more stages receiving lower significant bits of the compared value;
- implementing, for each stage, a first comparison function in a first lookup table;
- implementing, for each stage, a second comparison function in a second lookup table, the second comparison function different than the first comparison function;
- and
- using, for each stage receiving lower significant bits, an output of the first lookup table to select a result for the stage.
A device having programmable logic comprising a comparator, the device comprising:
- a plurality of comparator stages, each comparator stage comprising:
- a first comparison function and a second comparison function each coupled to receive a portion of a compared value, the second comparison function different than the first comparison function;
- and
- a selection circuit coupled to receive the output of the first comparison function at a selection input and an output of the second comparison function at an input;
- and
- an output coupled to the stage receiving most significant bits of the compared value and generating a result of the comparison.
Dependencies are inferred from the claim text.